Tutorials

  • Security of Quantum Computing Hardware and Architectures

    Monday | October 28, 2024 | 10:00 - 12:00

    This tutorial will introduce the audience to the emerging field of quantum computer security, which focuses on research on how to make quantum computing systems secure from attacks. By design, this tutorial will not cover post-quantum cryptography as that is an important, but orthogonal topic. The tutorial focuses on security of quantum computing systems as the rapid advances in quantum computer technologies, quantum computers hold promise to be able to run algorithms for generating novel drugs or material compounds. Once quantum computers are generating or processing sensitive data or valuable intellectual property, they will become a target for attacks that aim to disturb their operation, modify computation, or even try to steal data or quantum circuit code. Moreover, many quantum computers are already cloud-based and with remote, on-demand cloud access it makes them vulnerable to remote security attacks, no different from today’s classical cloud computing. 

  • Hardware Security and Trust Verification

    Monday | October 28, 2024 | 13:30 - 15:30

    System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable  hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in  the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints.  Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects  the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious  implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as  hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to  several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of  diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust  verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique.  While functional validation has received significant attention over the years, it is critical to perform “security and trust  verification” for designing trustworthy systems.

    • Prabhat Mishra.jpg

      University of Florida, USA

    • Farimah Farahmandi.jpg

      University of Florida, USA

  • Heterogeneous Integration: From physical layer to architecture and packaging

    Monday | October 28, 2024 | 16:00 - 18:00

    The growth of compute- and data-intensive applications has led to a search for new computing  architectures. General-purpose architectures such as CPUs, GPUs, often underperform compared to specialized accelerators  like TPUs that are tailored for specific tasks like machine learning. Despite the advantages of specialized accelerators, the  diversity in behavior among various emerging applications make it difficult to achieve good performance with one type of  architecture only. Heterogeneous architectures, that combine multiple types of general-purpose cores and various specialized  accelerators, are necessary to ensure that the computing platforms can support a variety of application such as AI, genomics,  graph analytics, etc. This embedded tutorial will present some of the challenges and opportunities in heterogeneous  architecture design starting from the physical layer, the design process for heterogeneous manycore architectures and  packaging techniques. It also presents a roadmap for open-source heterogeneous platforms, which will enable the research  community to innovate further. More specifically, this tutorial will address the following questions: 

    • Adrian.png

      CEA/LIST, France

    • Partha Pratim Pande.jpg

      Washington State University, USA

    • Chris Bailey.jpg

      Arizona State University, USA

  • Advanced Sparse Linear Solver for Transistor-Level Circuit Simulation

    Wednesday | October 30, 2024 | 13:30 - 15:30

    High-performance sparse linear solvers emerge as pivotal tools to facilitate rapid and accurate transistor-level circuit simulation and verification. Along with the fast development of semiconductor, modern integrated circuits (ICs) have been incredibly complex, consisting of hundreds of millions of components, causing sparse linear solvers to consume more time and memory resources for simulation. Furthermore, circuit matrices frequently exhibit high sparsity and non-uniform distributions of non-zero elements, compounding the chal lenge of achieving efficient acceleration. This tutorial proposes to delve into advanced sparse linear solving methodologies tailored specifically for transistor-level circuit simulation. We aim to explore state-of-the-art algorithms, optimizations, and parallelization strategies across various platforms, including CPUs, GPUs, and heterogeneous clusters to address the challenges posed by modern IC simulation. Practical implementation considerations and real-world case studies will be discussed to provide attendees with actionable insights into enhancing efficiency.

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      Xiaoming Chen

      Institute of Computing Technology, Chinese Academy of Sciences

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      Zhuo Feng

      Stevens Institute of Technology

    • Zhou Jin_ICCAD.png
      Zhou Jin

      China University of Petroleum-Beijing

    • Sheldon Tan.jpg

      University of California at Riverside, USA