Tutorials | ICCAD 2024

- Yale University, USA
Security of Quantum Computing Hardware and Architectures
Monday | October 28, 2024 | 10:00 - 12:00
This tutorial will introduce the audience to the emerging field of quantum computer security, which focuses on research on how to make quantum computing systems secure from attacks. By design, this tutorial will not cover post-quantum cryptography as that is an important, but orthogonal topic. The tutorial focuses on security of quantum computing systems as the rapid advances in quantum computer technologies, quantum computers hold promise to be able to run algorithms for generating novel drugs or material compounds. Once quantum computers are generating or processing sensitive data or valuable intellectual property, they will become a target for attacks that aim to disturb their operation, modify computation, or even try to steal data or quantum circuit code. Moreover, many quantum computers are already cloud-based and with remote, on-demand cloud access it makes them vulnerable to remote security attacks, no different from today’s classical cloud computing.
Hardware Security and Trust Verification
Monday | October 28, 2024 | 13:30 - 15:30
System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique. While functional validation has received significant attention over the years, it is critical to perform “security and trust verification” for designing trustworthy systems.
- University of Florida, USA
- University of Florida, USA
Heterogeneous Integration: From physical layer to architecture and packaging
Monday | October 28, 2024 | 16:00 - 18:00
The growth of compute- and data-intensive applications has led to a search for new computing architectures. General-purpose architectures such as CPUs, GPUs, often underperform compared to specialized accelerators like TPUs that are tailored for specific tasks like machine learning. Despite the advantages of specialized accelerators, the diversity in behavior among various emerging applications make it difficult to achieve good performance with one type of architecture only. Heterogeneous architectures, that combine multiple types of general-purpose cores and various specialized accelerators, are necessary to ensure that the computing platforms can support a variety of application such as AI, genomics, graph analytics, etc. This embedded tutorial will present some of the challenges and opportunities in heterogeneous architecture design starting from the physical layer, the design process for heterogeneous manycore architectures and packaging techniques. It also presents a roadmap for open-source heterogeneous platforms, which will enable the research community to innovate further. More specifically, this tutorial will address the following questions:
- CEA/LIST, France
- Washington State University, USA
- Arizona State University, USA
- University of California at Riverside, USA
Advanced Sparse Linear Solver for Transistor-Level Circuit Simulation
Wednesday | October 30, 2024 | 13:30 - 15:30
In this tutorial, I will discuss the recent advancements in the GLU based parallel sparse LU factorization solver GLU 3.0, which was developed at UC Riverside and open-sourced in 2019. I'll provide a brief overview of the development history of GLU solvers and their variants. LU factorization for sparse matrices is crucial for many engineering and scientific computing problems such as circuit simulation. However, parallelizing LU factorization on Graphic Processing Units (GPUs) poses challenges due to high data dependency and irregular memory access. To address this, GPU-based hybrid right-looking sparse LU solvers, GLU (1.0 and 2.0), were proposed to exploit fine-grained parallelism. However, they introduced a new data dependency (double-U dependency) which slowed down the pre-processing step, a problem fixed in GLU 2.0. Existing GLU solvers also employed a fixed thread allocation strategy, limiting parallelism exploration.