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style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.utdallas.edu/postings/27382\">\u003Cspan style=\"color:#1155cc;\">\u003Cu>Assistant and Associate Professor in Electrical and Computer Engineering\u003C/u>\u003C/span>\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:25.910Z","2024-10-26T20:57:21.210Z","2024-10-21T16:22:27.674Z","205",{"id":1144,"name":1145,"alternativeText":15,"caption":15,"width":1146,"height":1147,"formats":1148,"hash":1166,"ext":18,"mime":19,"size":1167,"url":1168,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1169,"updatedAt":1169},134,"monogram-emblem-border-880-1.png",880,587,{"small":1149,"medium":1155,"thumbnail":1160},{"ext":18,"url":1150,"hash":1151,"mime":19,"name":1152,"path":15,"size":1153,"width":648,"height":1154},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_monogram_emblem_border_880_1_8faf9d88be.png","small_monogram_emblem_border_880_1_8faf9d88be","small_monogram-emblem-border-880-1.png",22.25,334,{"ext":18,"url":1156,"hash":1157,"mime":19,"name":1158,"path":15,"size":1159,"width":655,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_monogram_emblem_border_880_1_8faf9d88be.png","medium_monogram_emblem_border_880_1_8faf9d88be","medium_monogram-emblem-border-880-1.png",35.91,{"ext":18,"url":1161,"hash":1162,"mime":19,"name":1163,"path":15,"size":1164,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_monogram_emblem_border_880_1_8faf9d88be.png","thumbnail_monogram_emblem_border_880_1_8faf9d88be","thumbnail_monogram-emblem-border-880-1.png",9.35,234,"monogram_emblem_border_880_1_8faf9d88be",7.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/monogram_emblem_border_880_1_8faf9d88be.png","2024-10-21T16:21:43.033Z",{"id":1171,"variation":595,"button":1172},61,[1173],{"id":212,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1174,"newWindow":8,"downloadable":15,"shape":15},"https://www.utdallas.edu/","-164",{"id":206,"name":1177,"description":1178,"createdAt":1179,"updatedAt":1180,"publishedAt":1181,"url_path_id":1182,"logo":1183,"website":1197,"url_path":1202},"Peking University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://drive.google.com/file/d/1Kh6kLqgXyZ-yHFcFpN0LtNoZA0l3s-bK/view?usp=drive_link\">Multiple tenure-track faculty positions\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:51.218Z","2024-10-26T20:55:41.318Z","2024-10-21T16:22:53.136Z","206",{"id":649,"name":1184,"alternativeText":15,"caption":15,"width":1185,"height":1102,"formats":1186,"hash":1193,"ext":18,"mime":19,"size":1194,"url":1195,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1196,"updatedAt":1196},"images (3).png",391,{"thumbnail":1187},{"ext":18,"url":1188,"hash":1189,"mime":19,"name":1190,"path":15,"size":1191,"width":589,"height":1192},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_3_68cbc0fd43.png","thumbnail_images_3_68cbc0fd43","thumbnail_images (3).png",17.77,81,"images_3_68cbc0fd43",7.83,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_3_68cbc0fd43.png","2024-10-21T16:21:42.687Z",{"id":1198,"variation":595,"button":1199},62,[1200],{"id":894,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1201,"newWindow":8,"downloadable":15,"shape":15},"https://english.pku.edu.cn/","-165",{"id":160,"name":1204,"description":45,"createdAt":1205,"updatedAt":1206,"publishedAt":1207,"url_path_id":1208,"logo":1209,"website":1231,"url_path":1235},"Chinese University of Hong Kong","2024-10-21T16:23:31.393Z","2024-10-21T16:25:07.701Z","2024-10-21T16:25:07.690Z","207",{"id":1210,"name":1211,"alternativeText":15,"caption":15,"width":1212,"height":1213,"formats":1214,"hash":1227,"ext":18,"mime":19,"size":1228,"url":1229,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1230,"updatedAt":1230},137,"cuhk_logo_2x.png",556,100,{"small":1215,"thumbnail":1221},{"ext":18,"url":1216,"hash":1217,"mime":19,"name":1218,"path":15,"size":1219,"width":648,"height":1220},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_cuhk_logo_2x_2674588b4f.png","small_cuhk_logo_2x_2674588b4f","small_cuhk_logo_2x.png",33.47,90,{"ext":18,"url":1222,"hash":1223,"mime":19,"name":1224,"path":15,"size":1225,"width":589,"height":1226},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_cuhk_logo_2x_2674588b4f.png","thumbnail_cuhk_logo_2x_2674588b4f","thumbnail_cuhk_logo_2x.png",11.33,44,"cuhk_logo_2x_2674588b4f",8.47,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/cuhk_logo_2x_2674588b4f.png","2024-10-21T16:25:04.093Z",{"id":946,"variation":595,"button":1232},[1233],{"id":335,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1234,"newWindow":8,"downloadable":15,"shape":15},"https://www.cuhk.edu.hk/","-166",{"id":310,"name":1237,"description":1238,"createdAt":1239,"updatedAt":1240,"publishedAt":1241,"url_path_id":1242,"logo":1243,"website":1276,"url_path":1280},"California State University, Long Beach","\u003Cp>Openings:\u003C/p>\u003Cp>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://careers.pageuppeople.com/873/lb/en-us/job/543010/assistant-professor-of-computer-science__;!!IKRxdwAv5BmarQ!eQj8K4F3IfjWIwE6lI2-CE4VMHwlbceaBpx6Qm-22ksIX6ZjXv3PrCSF51VgT13ifmtvdqiqtUzmU1Zx7gIuBOf2bWY$\">Assistant Professor of Computer Science\u003C/a>\u003C/p>","2024-10-21T16:25:34.926Z","2024-10-27T19:26:45.135Z","2024-10-21T16:25:37.001Z","208",{"id":1244,"name":1245,"alternativeText":15,"caption":15,"width":1246,"height":1247,"formats":1248,"hash":1273,"ext":18,"mime":19,"size":81,"url":1274,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1275,"updatedAt":1275},136,"49e1116896ee3dd71dd426fcd25cc16b.png",1280,800,{"large":1249,"small":1255,"medium":1261,"thumbnail":1267},{"ext":18,"url":1250,"hash":1251,"mime":19,"name":1252,"path":15,"size":1253,"width":640,"height":1254},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","large_49e1116896ee3dd71dd426fcd25cc16b.png",52.7,625,{"ext":18,"url":1256,"hash":1257,"mime":19,"name":1258,"path":15,"size":1259,"width":648,"height":1260},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","small_49e1116896ee3dd71dd426fcd25cc16b.png",23.09,313,{"ext":18,"url":1262,"hash":1263,"mime":19,"name":1264,"path":15,"size":1265,"width":655,"height":1266},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","medium_49e1116896ee3dd71dd426fcd25cc16b.png",37.06,469,{"ext":18,"url":1268,"hash":1269,"mime":19,"name":1270,"path":15,"size":1271,"width":589,"height":1272},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","thumbnail_49e1116896ee3dd71dd426fcd25cc16b.png",10.13,153,"49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","2024-10-21T16:21:43.178Z",{"id":396,"variation":595,"button":1277},[1278],{"id":316,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1279,"newWindow":8,"downloadable":15,"shape":15},"https://www.csulb.edu/","-167",{"id":227,"name":1282,"description":1283,"createdAt":1284,"updatedAt":1285,"publishedAt":1286,"url_path_id":1287,"logo":1288,"website":1320,"url_path":1325},"NVIDIA","\u003Cp>Openings:\u003C/p>\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/details/Research-Scientist--Design-Automation---New-College-Grad-2025_JR1989394-1?q=JR1989394\">Research scientist\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/PhD-Research-Intern--Robotics-and-or-Autonomous-Vehicles---2025_JR1989940-1?q=JR1989940+PhD+Research+Intern,+Robotics+and/or+Autonomous+Vehicles+-+2025\">Internship link\u003C/a>\u003C/li>\u003C/ul>","2024-10-21T16:26:10.208Z","2024-10-28T21:11:00.165Z","2024-10-21T16:26:12.361Z","209",{"id":1289,"name":1290,"alternativeText":15,"caption":15,"width":1291,"height":1292,"formats":1293,"hash":1316,"ext":18,"mime":19,"size":1317,"url":1318,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1319,"updatedAt":1319},135,"nvidia-logo-horz.png",1070,601,{"large":1294,"small":1300,"medium":1305,"thumbnail":1311},{"ext":18,"url":1295,"hash":1296,"mime":19,"name":1297,"path":15,"size":1298,"width":640,"height":1299},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_nvidia_logo_horz_e2054e7730.png","large_nvidia_logo_horz_e2054e7730","large_nvidia-logo-horz.png",39.87,562,{"ext":18,"url":1301,"hash":1302,"mime":19,"name":1303,"path":15,"size":1304,"width":648,"height":1034},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_nvidia_logo_horz_e2054e7730.png","small_nvidia_logo_horz_e2054e7730","small_nvidia-logo-horz.png",14.82,{"ext":18,"url":1306,"hash":1307,"mime":19,"name":1308,"path":15,"size":1309,"width":655,"height":1310},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_nvidia_logo_horz_e2054e7730.png","medium_nvidia_logo_horz_e2054e7730","medium_nvidia-logo-horz.png",25.1,421,{"ext":18,"url":1312,"hash":1313,"mime":19,"name":1314,"path":15,"size":1315,"width":589,"height":1046},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_nvidia_logo_horz_e2054e7730.png","thumbnail_nvidia_logo_horz_e2054e7730","thumbnail_nvidia-logo-horz.png",6.41,"nvidia_logo_horz_e2054e7730",8.64,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/nvidia_logo_horz_e2054e7730.png","2024-10-21T16:21:43.111Z",{"id":415,"variation":595,"button":1321},[1322],{"id":1323,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1324,"newWindow":8,"downloadable":15,"shape":15},73,"https://www.nvidia.com/en-us/","-168",{"id":247,"name":1327,"description":1328,"createdAt":1329,"updatedAt":1330,"publishedAt":1331,"url_path_id":1332,"logo":1333,"website":1353,"url_path":1358},"Arizona State University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://apply.interfolio.com/156770\">Professor (All Ranks) in Microelectronics\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:27:22.029Z","2024-10-26T20:56:24.414Z","2024-10-21T16:27:23.897Z","210",{"id":1334,"name":1335,"alternativeText":15,"caption":15,"width":1336,"height":1337,"formats":1338,"hash":1349,"ext":18,"mime":19,"size":1350,"url":1351,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1352,"updatedAt":1352},130,"images (4).png",512,98,{"small":1339,"thumbnail":1344},{"ext":18,"url":1340,"hash":1341,"mime":19,"name":1342,"path":15,"size":1343,"width":648,"height":766},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_images_4_722bb37608.png","small_images_4_722bb37608","small_images (4).png",33.41,{"ext":18,"url":1345,"hash":1346,"mime":19,"name":1347,"path":15,"size":1348,"width":589,"height":539},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_4_722bb37608.png","thumbnail_images_4_722bb37608","thumbnail_images (4).png",13.53,"images_4_722bb37608",6.12,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_4_722bb37608.png","2024-10-21T16:21:42.665Z",{"id":1055,"variation":595,"button":1354},[1355],{"id":1356,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1357,"newWindow":15,"downloadable":15,"shape":15},74,"https://www.asu.edu/","-169",{"id":509,"name":1360,"description":1361,"createdAt":1362,"updatedAt":1363,"publishedAt":1364,"url_path_id":1365,"logo":1366,"website":1386,"url_path":1390},"University of Wisconsin","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.wisc.edu/jobs/professor-open-rank-in-electrical-computer-engineering-ai-for-chip-design-madison-wisconsin-united-states\">Professor (open rank) in Electrical & Computer Engineering - AI for Chip Design\u003C/a>\u003C/li>\u003C/ol>\u003Cp> \u003C/p>\u003Cp> \u003C/p>","2024-10-21T16:28:02.562Z","2024-10-26T20:56:56.929Z","2024-10-21T16:28:04.775Z","211",{"id":1367,"name":1368,"alternativeText":15,"caption":15,"width":1369,"height":1370,"formats":1371,"hash":1383,"ext":18,"mime":19,"size":180,"url":1384,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1385,"updatedAt":1385},132,"vert-w-crest-logo-web-digital-color.png",600,400,{"small":1372,"thumbnail":1378},{"ext":18,"url":1373,"hash":1374,"mime":19,"name":1375,"path":15,"size":1376,"width":648,"height":1377},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_vert_w_crest_logo_web_digital_color_beb0805fb0.png","small_vert_w_crest_logo_web_digital_color_beb0805fb0","small_vert-w-crest-logo-web-digital-color.png",62.38,333,{"ext":18,"url":1379,"hash":1380,"mime":19,"name":1381,"path":15,"size":1382,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0.png","thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0","thumbnail_vert-w-crest-logo-web-digital-color.png",20.47,"vert_w_crest_logo_web_digital_color_beb0805fb0","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/vert_w_crest_logo_web_digital_color_beb0805fb0.png","2024-10-21T16:21:42.813Z",{"id":520,"variation":595,"button":1387},[1388],{"id":233,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1389,"newWindow":8,"downloadable":15,"shape":15},"https://www.wisc.edu/","-170",{"id":200,"name":1392,"description":45,"createdAt":1393,"updatedAt":1394,"publishedAt":1395,"url_path_id":1396,"logo":1397,"website":1425,"url_path":1429},"Villanova University","2024-10-26T11:20:53.250Z","2024-10-26T11:20:55.579Z","2024-10-26T11:20:55.572Z","212",{"id":1046,"name":1398,"alternativeText":15,"caption":15,"width":1246,"height":1399,"formats":1400,"hash":1421,"ext":760,"mime":763,"size":1422,"url":1423,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1424,"updatedAt":1424},"image_1579638630.no.size.img.jpg",960,{"large":1401,"small":1406,"medium":1411,"thumbnail":1416},{"ext":760,"url":1402,"hash":1403,"mime":763,"name":1404,"path":15,"size":1405,"width":640,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_image_1579638630_no_size_img_0c4aefb873.jpg","large_image_1579638630_no_size_img_0c4aefb873","large_image_1579638630.no.size.img.jpg",34.67,{"ext":760,"url":1407,"hash":1408,"mime":763,"name":1409,"path":15,"size":1410,"width":648,"height":1079},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_image_1579638630_no_size_img_0c4aefb873.jpg","small_image_1579638630_no_size_img_0c4aefb873","small_image_1579638630.no.size.img.jpg",13.1,{"ext":760,"url":1412,"hash":1413,"mime":763,"name":1414,"path":15,"size":1415,"width":655,"height":1028},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_image_1579638630_no_size_img_0c4aefb873.jpg","medium_image_1579638630_no_size_img_0c4aefb873","medium_image_1579638630.no.size.img.jpg",22.85,{"ext":760,"url":1417,"hash":1418,"mime":763,"name":1419,"path":15,"size":1420,"width":621,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_image_1579638630_no_size_img_0c4aefb873.jpg","thumbnail_image_1579638630_no_size_img_0c4aefb873","thumbnail_image_1579638630.no.size.img.jpg",3.51,"image_1579638630_no_size_img_0c4aefb873",49.04,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/image_1579638630_no_size_img_0c4aefb873.jpg","2024-10-26T11:20:33.114Z",{"id":1133,"variation":595,"button":1426},[1427],{"id":16,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1428,"newWindow":15,"downloadable":15,"shape":15},"https://www1.villanova.edu/university.html","-171",{"id":324,"name":1431,"description":45,"createdAt":1432,"updatedAt":1433,"publishedAt":1434,"url_path_id":1435,"logo":1436,"website":1450,"url_path":1455},"Syracuse University","2024-10-26T18:34:30.431Z","2024-10-26T18:35:05.768Z","2024-10-26T18:35:05.761Z","213",{"id":1437,"name":1438,"alternativeText":15,"caption":15,"width":1439,"height":649,"formats":1440,"hash":1446,"ext":18,"mime":19,"size":1447,"url":1448,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1449,"updatedAt":1449},139,"images (5).png",384,{"thumbnail":1441},{"ext":18,"url":1442,"hash":1443,"mime":19,"name":1444,"path":15,"size":1445,"width":589,"height":582},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_5_292bd7738d.png","thumbnail_images_5_292bd7738d","thumbnail_images (5).png",12.99,"images_5_292bd7738d",4.92,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_5_292bd7738d.png","2024-10-26T18:34:09.860Z",{"id":212,"variation":595,"button":1451},[1452],{"id":1453,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1454,"newWindow":8,"downloadable":15,"shape":15},77,"https://www.syracuse.edu/","-172",{"pagination":1457},{"page":5,"pageSize":324,"pageCount":27,"total":102},{"id":247,"heading":242,"pageHeader":1459,"sections":1461},{"id":247,"description":1460,"showPageHeader":8,"backgroundColor":49,"image":15}," ",[1462],{"id":74,"__component":1463,"componentVariation":1464,"contactsVariation":1465,"styles":15,"header":15,"sessionsGroup":1466},"content.sessions","Sessions Base","Card Contact Full",[1467],{"id":74,"groupTitle":15,"sessions":1468},[1469,1502,1591,1706],{"id":409,"session":1470},{"id":409,"title":1471,"teaser":1472,"body":1473,"createdAt":1474,"updatedAt":1475,"publishedAt":1476,"url_path_id":1477,"contacts":1478,"url_path":1501},"Security of Quantum Computing Hardware and Architectures","\u003Ch4 class=\"h4\" style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:rgb(83,127,154);\">\u003Cstrong>Monday | October 28, 2024 | 10:00 - 12:00\u003C/strong>\u003C/span>\u003C/h4>\u003Cp style=\"text-align:justify;\">This tutorial will introduce the audience to the emerging field of quantum computer security, which focuses on research on how to make quantum computing systems secure from attacks. By design, this tutorial will not cover post-quantum cryptography as that is an important, but orthogonal topic. The tutorial focuses on security of quantum computing systems as the rapid advances in quantum computer technologies, quantum computers hold promise to be able to run algorithms for generating novel drugs or material compounds. Once quantum computers are generating or processing sensitive data or valuable intellectual property, they will become a target for attacks that aim to disturb their operation, modify computation, or even try to steal data or quantum circuit code. Moreover, many quantum computers are already cloud-based and with remote, on-demand cloud access it makes them vulnerable to remote security attacks, no different from today’s classical cloud computing. \u003C/p>","\u003Cp style=\"text-align:justify;\">First, this tutorial will introduce audience to classical computer security ideas such as threat modeling, confidentiality, integrity, and availability, information leaks, side- and covert-channel attacks. Second, this tutorial will demonstrate examples of security attacks prototyped on real cloud based NISQ quantum computers available today. Third, the tutorial will present designs for securing the cloud based NISQ quantum computers from the security attacks. Lastly, the tutorial will present challenges and opportunities to build quantum computer security from the ground up, rather than patch them later once security attacks have occurred in the wild.\u003C/p>","2024-07-11T19:52:21.223Z","2024-08-23T13:01:36.907Z","2024-07-11T19:52:22.896Z","94",[1479],{"id":200,"name":1480,"committee":15,"position":15,"affiliation":1481,"email":15,"biography":1482,"createdAt":1483,"updatedAt":1483,"url_path_id":1484,"contactPhoto":1485,"socialLinks":1499,"url_path":1500},"Jakub Szefer","Yale University, USA","\u003Cp style=\"text-align:justify;\">Prof. Jakub Szefer is currently an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). Jakub’s research encompasses secure processor architectures, cloud and device security, fast implementation of post-quantum cryptographic algorithms, as well as quantum computer cybersecurity. Among others, Jakub is the author of first book focusing on processor architecture security: “Principles of Secure Processor Architecture Design”, published in 2018. Most recently, Jakub is a recipient of the 2021 Ackerman Award for Teaching and Mentoring from Yale University. He has published numerous security papers on quantum computing in top venues such as HOST and CCS.\u003C/p>","2024-07-11T19:50:58.866Z","93",{"id":316,"name":1486,"alternativeText":15,"caption":15,"width":1370,"height":1487,"formats":1488,"hash":1495,"ext":760,"mime":763,"size":1496,"url":1497,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1498,"updatedAt":1498},"Jakub Szefer.jpg",423,{"thumbnail":1489},{"ext":760,"url":1490,"hash":1491,"mime":763,"name":1492,"path":15,"size":1493,"width":1494,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Jakub_Szefer_4b1af59bae.jpg","thumbnail_Jakub_Szefer_4b1af59bae","thumbnail_Jakub Szefer.jpg",4.82,148,"Jakub_Szefer_4b1af59bae",30.6,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Jakub_Szefer_4b1af59bae.jpg","2024-07-11T19:50:55.141Z",[],"-68","-69",{"id":81,"session":1503},{"id":81,"title":1504,"teaser":1505,"body":1506,"createdAt":1507,"updatedAt":1508,"publishedAt":1509,"url_path_id":1510,"contacts":1511,"url_path":1590},"Hardware Security and Trust Verification","\u003Ch4 class=\"h4\" style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:rgb(83,127,154);\">\u003Cstrong>Monday | October 28, 2024 | 13:30 - 15:30\u003C/strong>\u003C/span>\u003C/h4>\u003Cp style=\"text-align:justify;\">System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems. Reusable  hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in  the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints.  Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects  the security and trustworthiness of SoC computing platforms. These third-party IPs may come with deliberate malicious  implants to incorporate undesired functionality (e.g., hardware Trojans), undocumented test/debug interface working as  hidden backdoor, or other integrity issues. It is extremely difficult to verify integrity and trust of hardware IPs due to  several reasons including (a) lack of a golden reference model or incomplete specification, (b) exponential space of  diverse types of complex IPs and IP-specific vulnerabilities, (c) lack of automated and scalable CAD tools for IP trust  verification, and (d) lack of security metrics to measure the security robustness of a given design or mitigation technique.  While functional validation has received significant attention over the years, it is critical to perform “security and trust  verification” for designing trustworthy systems.\u003C/p>","\u003Cp style=\"text-align:justify;\">\u003Cspan style=\"background-color:transparent;color:#000000;\">This tutorial will provide a comprehensive overview of both fundamental concepts and recent advances in hardware  security and trust validation using simulation-based approaches, formal methods as well as side-channel analysis. Specifically, the tutorial will consist of five parts. The first part will introduce security vulnerabilities (threats) and  various challenges associated with trust validation of hardware IPs. It will highlight recent advances in developing trust  metrics and benchmarks. The second part will cover assertion-based security validation utilizing automated generation  of security assertions. It will also cover automated test generation techniques (including directed tests, fuzz tests, and  penetration tests) for activation of security assertions. The third part will describe how formal verification techniques (including model checking, SAT solving, theorem proving and equivalence checking) can be effectively utilized for  validation of hardware security vulnerabilities. The fourth part discusses the use of machine learning and AI-assisted  techniques to facilitate security verification efforts. The fifth part will discuss how side-channel analysis can be  effectively utilized to detect malicious implants. It will conclude with a discussion on integration of security verification  in existing functional validation methodology. \u003C/span>\u003C/p>","2024-07-11T19:35:48.796Z","2024-08-23T12:48:20.739Z","2024-07-11T19:35:50.988Z","85",[1512,1554],{"id":310,"name":1513,"committee":15,"position":15,"affiliation":1514,"email":15,"biography":1515,"createdAt":1516,"updatedAt":1517,"url_path_id":1518,"contactPhoto":1519,"socialLinks":1552,"url_path":1553},"Prabhat Mishra","University of Florida, USA","\u003Cp style=\"text-align:justify;\">Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the  University of Florida. His research interests include embedded and cyber-physical systems, hardware security and trust,  energy-aware computing, formal verification, system-on-chip validation, and post-silicon debug. Prior to joining  University of Florida, he spent several years in various companies including Intel, Motorola, Sasken, Synopsys and  Texas Instruments. He has published 9 books, 35 book chapters, several patents/copyrights, and more than 250 research  articles in premier international journals and conferences. His research has been recognized by several awards including  the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, three Best Paper Awards  (ISQED'16, VLSID'11 and CODES+ISSS'03) as well as eight Best Paper Nominations, and EDAA Outstanding  Dissertation Award from the European Design Automation Association. Prof. Mishra currently serves as an Associate  Editor of ACM Transactions of Embedded Computing Systems and ACM Transactions on Design Automation of  Electronic Systems. He has served as the Deputy Editor-in-Chief of IET Computer & Digital Techniques, and as an  Associate Editor of IEEE Transactions on VLSI Systems, and IEEE Design & Test, and Springer Journal of Electronic  Testing. He is an IEEE Fellow, a Fellow of the American Association for the Advancement of Science (AAAS), and an ACM Distinguished Scientist. \u003C/p>","2024-07-11T19:37:59.653Z","2024-07-11T20:02:39.558Z","86",{"id":212,"name":1520,"alternativeText":15,"caption":15,"width":1521,"height":1522,"formats":1523,"hash":1547,"ext":760,"mime":763,"size":1548,"url":1549,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1550,"updatedAt":1551},"Prabhat Mishra.jpg",1925,1952,{"large":1524,"small":1530,"medium":1536,"thumbnail":1542},{"ext":760,"url":1525,"hash":1526,"mime":763,"name":1527,"path":15,"size":1528,"width":1529,"height":640},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_Prabhat_Mishra_24487cf5b0.jpg","large_Prabhat_Mishra_24487cf5b0","large_Prabhat Mishra.jpg",103.9,986,{"ext":760,"url":1531,"hash":1532,"mime":763,"name":1533,"path":15,"size":1534,"width":1535,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Prabhat_Mishra_24487cf5b0.jpg","small_Prabhat_Mishra_24487cf5b0","small_Prabhat Mishra.jpg",28.5,493,{"ext":760,"url":1537,"hash":1538,"mime":763,"name":1539,"path":15,"size":1540,"width":1541,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Prabhat_Mishra_24487cf5b0.jpg","medium_Prabhat_Mishra_24487cf5b0","medium_Prabhat Mishra.jpg",59.8,740,{"ext":760,"url":1543,"hash":1544,"mime":763,"name":1545,"path":15,"size":1546,"width":1272,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Prabhat_Mishra_24487cf5b0.jpg","thumbnail_Prabhat_Mishra_24487cf5b0","thumbnail_Prabhat Mishra.jpg",4.6,"Prabhat_Mishra_24487cf5b0",374.34,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Prabhat_Mishra_24487cf5b0.jpg","2024-07-11T19:37:56.434Z","2024-07-11T20:02:38.576Z",[],"-62",{"id":227,"name":1555,"committee":15,"position":15,"affiliation":1514,"email":15,"biography":1556,"createdAt":1557,"updatedAt":1558,"url_path_id":1559,"contactPhoto":1560,"socialLinks":1588,"url_path":1589},"Farimah Farahmandi","\u003Cp style=\"text-align:justify;\">Farimah Farahmandi is Yangbin Wang Rising Star Endowed Assistant Professor in the Department of Electrical and  Computer Engineering (ECE) and the associate director of the Florida Institute for Cybersecurity (FICS) at the University  of Florida. Her research interests include hardware security verification, formal methods, and post-silicon validation. \u003C/p>\u003Cp style=\"text-align:justify;\">Her research has resulted in seven books, nine book chapters, and several publications in premier ACM/IEEE journals  and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation  Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several  awards including the 2022 Semiconductor Research Corporation Young Faculty Award, the 2022 ECE Research  Excellence Award, and 2023 ECE Service Excellence Award at UF. She is also the recipient of four best paper  nominations from IEEE/ACM ASP-DAC and IEEE/ACM DATE. She is one of the co-founders of CAD4Sec Workshop.  Currently, she is the program chair of IEEE HOST 2024. Her research has been sponsored by NSF, SRC, DARPA,  AFRL, DoD, ONR, Analog Devices, ANSYS, Synopsys, and Cisco. \u003C/p>","2024-07-11T19:39:37.480Z","2024-07-11T20:02:15.391Z","87",{"id":894,"name":1561,"alternativeText":15,"caption":15,"width":1562,"height":1563,"formats":1564,"hash":1583,"ext":760,"mime":763,"size":1584,"url":1585,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1586,"updatedAt":1587},"Farimah Farahmandi.jpg",824,818,{"small":1565,"medium":1571,"thumbnail":1577},{"ext":760,"url":1566,"hash":1567,"mime":763,"name":1568,"path":15,"size":1569,"width":648,"height":1570},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Farimah_Farahmandi_e7cca8510f.jpg","small_Farimah_Farahmandi_e7cca8510f","small_Farimah Farahmandi.jpg",30.55,496,{"ext":760,"url":1572,"hash":1573,"mime":763,"name":1574,"path":15,"size":1575,"width":655,"height":1576},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Farimah_Farahmandi_e7cca8510f.jpg","medium_Farimah_Farahmandi_e7cca8510f","medium_Farimah Farahmandi.jpg",60.9,745,{"ext":760,"url":1578,"hash":1579,"mime":763,"name":1580,"path":15,"size":1581,"width":1582,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Farimah_Farahmandi_e7cca8510f.jpg","thumbnail_Farimah_Farahmandi_e7cca8510f","thumbnail_Farimah Farahmandi.jpg",4.47,158,"Farimah_Farahmandi_e7cca8510f",71.75,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Farimah_Farahmandi_e7cca8510f.jpg","2024-07-11T19:39:34.557Z","2024-07-11T20:02:14.013Z",[],"-63","-61",{"id":166,"session":1592},{"id":390,"title":1593,"teaser":1594,"body":1595,"createdAt":1596,"updatedAt":1597,"publishedAt":1598,"url_path_id":1599,"contacts":1600,"url_path":1705},"Heterogeneous Integration: From physical layer to architecture and packaging","\u003Ch4 class=\"h4\" style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:rgb(83,127,154);\">\u003Cstrong>Monday | October 28, 2024 | 16:00 - 18:00\u003C/strong>\u003C/span>\u003C/h4>\u003Cp style=\"text-align:justify;\">The growth of compute- and data-intensive applications has led to a search for new computing  architectures. General-purpose architectures such as CPUs, GPUs, often underperform compared to specialized accelerators  like TPUs that are tailored for specific tasks like machine learning. Despite the advantages of specialized accelerators, the  diversity in behavior among various emerging applications make it difficult to achieve good performance with one type of  architecture only. Heterogeneous architectures, that combine multiple types of general-purpose cores and various specialized  accelerators, are necessary to ensure that the computing platforms can support a variety of application such as AI, genomics,  graph analytics, etc. This embedded tutorial will present some of the challenges and opportunities in heterogeneous  architecture design starting from the physical layer, the design process for heterogeneous manycore architectures and  packaging techniques. It also presents a roadmap for open-source heterogeneous platforms, which will enable the research  community to innovate further. More specifically, this tutorial will address the following questions: \u003C/p>","\u003Cp style=\"text-align:justify;\">(1) What are some  important physical layer considerations in heterogeneous architectures? (2) What are some of the important challenges  associated with the design and optimization of heterogeneous architectures with in-memory computing support? (3) What  are the challenges associated with packaging a heterogeneous IC? To address these key questions, out-of-the-box approaches  need to be explored. By integrating ML algorithms, data analytics, 2.5D integration, statistical modeling, this tutorial will  engage a broad section of ICCAD conference attendees. Specifically, this tutorial has a good balance between diverse topics  associated with heterogeneous integration, and with global footprint. It is targeted towards university researchers/professors,  students, industry professionals, and computing system designers. It will attract newcomers who want to learn about heterogeneous architectures. Simultaneously, this tutorial will act as a catalyst for experienced researchers looking for  exciting new directions in hardware design, packaging, and open-source architectures. The title of each presentation (each  presenter has confirmed their participation) and the associated paper along with the names of the authors are as follows:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli style=\"text-align:justify;\">\u003Cstrong>OpenSource Heterogeneous Chiplet-based Computing Architectures:\u003C/strong> (Presenter: Adrian Evans (CEA), co authors: César Fuguet (CEA), Davy Million (CEA): Leading edge processors, such as AMD’s CDNA 3, rely on 3D  integration of heterogeneous architectures including CPUs and GPUs to provide the highest performance. There are  many models for memory coherency within such chips and there is a need for research on the best way to map various  kernels to these architectures including studying how best to share data. Unfortunately, the hardware in commercial  processors is closed, which limits research opportunities. Recent projects such as OpenPiton, and numerous follow-on  projects, have made it possible for the research community to easily develop coherent, multi-core systems based on  RISC-V. The next step is to enhance the support in open-source, multi-core platforms for heterogeneous compute  (GPUs, FPGA accelerators) and to explore 3D partitioning of such systems. We will present a roadmap for such open source platforms which we believe are important to enable the research community to continue to contribute to the  development of today’s advanced, heterogeneous architectures.\u003C/li>\u003Cli style=\"text-align:justify;\">\u003Cstrong>Heterogeneous manycore in-memory computing architectures: \u003C/strong>(Presenter: Partha Pratim Pande, Washington  State University, co-authors: Biresh Joardar, University of Houston, Chukwufumnanya Ogbogu, Gaurav Narang, Jana  Doppa, Washington State University): The growing use of deep learning has led to an increasing demand for hardware platforms that are computationally powerful, yet energy-efficient. In-memory computing (IMC) architectures using  non-volatile memory, such as resistive random-access memory (ReRAM), present a promising alternative. However,  IMCs lack general purpose computing capability. For instance, ReRAM crossbars are not suited for high-throughput  division, which is needed for implementing the batch normalization layers [4]. Similarly, GPUs can perform division operations, but they are significantly slower than ReRAM crossbars for multiplications, which form the primary  backbone of most AI algorithms. However, in addition to ReRAM, there are a plethora of IMC devices, and they offer advantages and drawbacks in terms power, latency, area, and non-idealities. In this talk, we present an architecture that  combines both in an optimized manner to derive the best out of both worlds (IMC and general-purpose computing). The architecture combines the high-throughput multiplications of IMCs with the general-purpose computing ability of  floating-point devices (such as CPU, GPU, etc.) to implement both training and inferencing of various AI algorithms.  The computing units are enabled by additional DRAM memory tiles. All the tiles are in turn connected via a Network on-chip (NoC) for high-throughput communication support.  \u003C/li>\u003Cli style=\"text-align:justify;\">\u003Cstrong>Package modeling and analysis for Heterogeneous Integration: \u003C/strong>(Presenter: Chris Bailey, Arizona State University,  co-authors: Leslie Hwang, Pallavi Praful, Arizona State University): Advanced semiconductor packaging is now used  by semiconductors companies to meet the requirements (e.g. bandwidth, latency, power, etc.) for AI applications using  heterogeneous multi-chiplet architectures. These packaging techniques include flip-chip, wafer-level packaging (both  fan-in and fan-out) and 3D-Heterogeneous Integration (3D-HI) using package-on-package and hybrid/direct bonding.  As detailed in roadmaps such as the Heterogeneous Integration Roadmap (HIR) and the SRC Microelectronics and  Packaging Technology (MAPT), chip-package-board co-design supported by multi-physics modeling and analysis are  key underpinning technologies. This presentation will discuss the current state of the art in Co-Design and Multi Physics Analysis for advanced semiconductor packaging. Examples will demonstrate how such modelling techniques  have informed package design-space exploration for materials selection (e.g. mold compounds in a wafer level package)  as well as predicting warpage, electromigration, interconnect fatigue, and redistribution layer (RDL) delamination. For  design-space exploration examples of fast modelling predictions and their accuracy will also be demonstrated using  techniques such as model-order reduction and physics informed AI. The paper will also detail the current challenges  faced by EDA tools for system-level cross-domain design flows informed by integrated multi-physics models for multi chiplet architectures that address the packaging architecture requirements for ultra-high-density RDL line/spacing  (<1um) and fine pitch assembly (<2um). \u003C/li>\u003C/ol>","2024-07-11T19:47:43.640Z","2024-08-23T12:49:28.021Z","2024-07-11T19:47:45.211Z","91",[1601,1644,1680],{"id":509,"name":1602,"committee":15,"position":15,"affiliation":1603,"email":15,"biography":1604,"createdAt":1605,"updatedAt":1606,"url_path_id":1607,"contactPhoto":1608,"socialLinks":1642,"url_path":1643},"Adrian Evans","CEA/LIST, France","\u003Cp style=\"text-align:justify;\">Adrian Evans has been with the CEA/LIST for six years and his research interests include fault tolerance, high performance computing and 3D integration. Previously, he worked at Cisco Systems for twelve years as a designer of  ASICs for high-end routers. At CEA/LIST he has participated in the design of a complex 3D circuit. He is a member  of the IEEE P3405 working group on 3D interconnect and repair. He has a PhD from Grenoble Alpes University and  he is the author or co-author of forty scientific publications. \u003C/p>","2024-07-11T19:49:15.740Z","2024-07-19T17:42:38.050Z","92",{"id":1609,"name":1610,"alternativeText":15,"caption":15,"width":1611,"height":1612,"formats":1613,"hash":1638,"ext":18,"mime":19,"size":1639,"url":1640,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1641,"updatedAt":1641},107,"Adrian.png",1431,1425,{"large":1614,"small":1620,"medium":1626,"thumbnail":1632},{"ext":18,"url":1615,"hash":1616,"mime":19,"name":1617,"path":15,"size":1618,"width":640,"height":1619},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_Adrian_db81c0abde.png","large_Adrian_db81c0abde","large_Adrian.png",1444.08,996,{"ext":18,"url":1621,"hash":1622,"mime":19,"name":1623,"path":15,"size":1624,"width":648,"height":1625},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Adrian_db81c0abde.png","small_Adrian_db81c0abde","small_Adrian.png",401.21,498,{"ext":18,"url":1627,"hash":1628,"mime":19,"name":1629,"path":15,"size":1630,"width":655,"height":1631},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Adrian_db81c0abde.png","medium_Adrian_db81c0abde","medium_Adrian.png",853.67,747,{"ext":18,"url":1633,"hash":1634,"mime":19,"name":1635,"path":15,"size":1636,"width":1637,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Adrian_db81c0abde.png","thumbnail_Adrian_db81c0abde","thumbnail_Adrian.png",46.81,157,"Adrian_db81c0abde",627.42,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Adrian_db81c0abde.png","2024-07-19T17:42:34.781Z",[],"-67",{"id":324,"name":1645,"committee":15,"position":15,"affiliation":1646,"email":15,"biography":1647,"createdAt":1648,"updatedAt":1648,"url_path_id":1649,"contactPhoto":1650,"socialLinks":1678,"url_path":1679},"Partha Pratim Pande","Washington State University, USA","\u003Cp style=\"text-align:justify;\">Partha Pratim Pande is a professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. His current research  interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks,  heterogeneous architectures, and ML for EDA. Dr. Pande currently serves as the Editor-in-Chief (EIC) of IEEE Design  and Test (D&T). He has won the NSF CAREER award in 2009. He is a fellow of IEEE. \u003C/p>","2024-07-11T20:00:04.908Z","95",{"id":1356,"name":1651,"alternativeText":15,"caption":15,"width":1652,"height":1653,"formats":1654,"hash":1673,"ext":760,"mime":763,"size":1674,"url":1675,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1676,"updatedAt":1677},"Partha Pratim Pande.jpg",912,878,{"small":1655,"medium":1661,"thumbnail":1667},{"ext":760,"url":1656,"hash":1657,"mime":763,"name":1658,"path":15,"size":1659,"width":648,"height":1660},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Partha_Pratim_Pande_d9a6438583.jpg","small_Partha_Pratim_Pande_d9a6438583","small_Partha Pratim Pande.jpg",41.79,481,{"ext":760,"url":1662,"hash":1663,"mime":763,"name":1664,"path":15,"size":1665,"width":655,"height":1666},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Partha_Pratim_Pande_d9a6438583.jpg","medium_Partha_Pratim_Pande_d9a6438583","medium_Partha Pratim Pande.jpg",89.93,722,{"ext":760,"url":1668,"hash":1669,"mime":763,"name":1670,"path":15,"size":1671,"width":1672,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Partha_Pratim_Pande_d9a6438583.jpg","thumbnail_Partha_Pratim_Pande_d9a6438583","thumbnail_Partha Pratim Pande.jpg",6.03,162,"Partha_Pratim_Pande_d9a6438583",130.42,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Partha_Pratim_Pande_d9a6438583.jpg","2024-07-11T19:59:46.253Z","2024-07-11T20:00:03.392Z",[],"-70",{"id":102,"name":1681,"committee":15,"position":15,"affiliation":1682,"email":15,"biography":1683,"createdAt":1684,"updatedAt":1684,"url_path_id":1685,"contactPhoto":1686,"socialLinks":1703,"url_path":1704},"Chris Bailey","Arizona State University, USA","\u003Cp style=\"text-align:justify;\">Chris Bailey joined Arizona State University in 2022. He is Director of the Advanced Semiconductor Packaging Centre  and Professor in Electronics Packaging and Reliability. Before joining ASU, he was Associated Dean for Research at  the University of Greenwich, UK. He has published 400+ archival papers, and from 2020-2021 was the President of  the IEEE Electronics Packaging Society. He also serves on the Heterogeneous Integration Roadmap as chapter co-chair  for the Co-Design and Modelling and Simulation Chapters.\u003C/p>","2024-07-11T20:01:13.367Z","96",{"id":233,"name":1687,"alternativeText":15,"caption":15,"width":1369,"height":1369,"formats":1688,"hash":1699,"ext":760,"mime":763,"size":1700,"url":1701,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1702,"updatedAt":1702},"Chris Bailey.jpg",{"small":1689,"thumbnail":1694},{"ext":760,"url":1690,"hash":1691,"mime":763,"name":1692,"path":15,"size":1693,"width":648,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Chris_Bailey_01cf6cfe9d.jpg","small_Chris_Bailey_01cf6cfe9d","small_Chris Bailey.jpg",26.96,{"ext":760,"url":1695,"hash":1696,"mime":763,"name":1697,"path":15,"size":1698,"width":622,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Chris_Bailey_01cf6cfe9d.jpg","thumbnail_Chris_Bailey_01cf6cfe9d","thumbnail_Chris Bailey.jpg",4.64,"Chris_Bailey_01cf6cfe9d",35.93,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Chris_Bailey_01cf6cfe9d.jpg","2024-07-11T20:01:11.053Z",[],"-71","-66",{"id":390,"session":1707},{"id":166,"title":1708,"teaser":1709,"body":1710,"createdAt":1711,"updatedAt":1712,"publishedAt":1713,"url_path_id":1714,"contacts":1715,"url_path":1817},"Advanced Sparse Linear Solver for Transistor-Level Circuit Simulation","\u003Ch4 class=\"h4\" style=\"margin-left:0px;text-align:justify;\">\u003Cspan style=\"color:rgb(83,127,154);\">\u003Cstrong>Wednesday | October 30, 2024 | 13:30 - 15:30\u003C/strong>\u003C/span>\u003C/h4>\u003Cp style=\"text-align:justify;\">High-performance sparse linear solvers emerge as pivotal tools to facilitate rapid and accurate transistor-level circuit simulation and verification. Along with the fast development of semiconductor, modern integrated circuits (ICs) have been incredibly complex, consisting of hundreds of millions of components, causing sparse linear solvers to consume more time and memory resources for simulation. Furthermore, circuit matrices frequently exhibit high sparsity and non-uniform distributions of non-zero elements, compounding the chal lenge of achieving efficient acceleration. This tutorial proposes to delve into advanced sparse linear solving methodologies tailored specifically for transistor-level circuit simulation. We aim to explore state-of-the-art algorithms, optimizations, and parallelization strategies across various platforms, including CPUs, GPUs, and heterogeneous clusters to address the challenges posed by modern IC simulation. Practical implementation considerations and real-world case studies will be discussed to provide attendees with actionable insights into enhancing efficiency.\u003C/p>","\u003Cp style=\"text-align:justify;\">This tutorial features four speakers, each with substantial expertise in sparse linear solver algorithms and software development tailored to circuit simulation. The first talk will introduce GLU3.0, an open source GPU-based sparse linear solver developed at UC Riverside, which can dynamically allocate GPU blocks and wraps, better balancing computing demands and resources. The second talk will show CKTSO, a high perfor mance sparse linear solver on multi-core shared memory computer, including various innovations, e.g., matrix reordering, LU factorization with pivot check, structure-adaptive hybrid parallel triangular solving, etc. The third talk will present the machine learning-enhanced spare linear solver considering the irregular sparsity distribution characteristics for circuit simulation and synchronization-free acceleration on GPU and distributed heterogeneous clusters. The final talk will focus on leveraging spectral graph sparsification techniques to ac celerate the modeling and simulation of large-scale integrated circuits, addressing the computational challenges posed by the increasing complexity of modern IC simulation. This tutorial welcomes designers, researchers, and developers from both industry and academia who are seeking to advance the performance of sparse linear solver for circuit simulation and verification to a new level previously out of reach. \u003C/p>","2024-07-11T19:42:21.160Z","2024-10-18T15:10:42.185Z","2024-07-11T19:42:22.791Z","89",[1716,1738,1771,1793],{"id":335,"name":1717,"committee":15,"position":15,"affiliation":1718,"email":15,"biography":45,"createdAt":1719,"updatedAt":1719,"url_path_id":1720,"contactPhoto":1721,"socialLinks":1736,"url_path":1737},"Xiaoming Chen","Institute of Computing Technology, Chinese Academy of Sciences","2024-10-18T15:08:57.727Z","201",{"id":1722,"name":1723,"alternativeText":15,"caption":15,"width":1724,"height":1725,"formats":1726,"hash":1732,"ext":18,"mime":19,"size":1733,"url":1734,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1735,"updatedAt":1735},126,"Xiaoming Chen_ICCAD.png",246,328,{"thumbnail":1727},{"ext":18,"url":1728,"hash":1729,"mime":19,"name":1730,"path":15,"size":1731,"width":837,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Xiaoming_Chen_ICCAD_e8d854495b.png","thumbnail_Xiaoming_Chen_ICCAD_e8d854495b","thumbnail_Xiaoming Chen_ICCAD.png",41.23,"Xiaoming_Chen_ICCAD_e8d854495b",39.78,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Xiaoming_Chen_ICCAD_e8d854495b.png","2024-10-18T15:08:07.047Z",[],"-160",{"id":1323,"name":1739,"committee":15,"position":15,"affiliation":1740,"email":15,"biography":45,"createdAt":1741,"updatedAt":1741,"url_path_id":1742,"contactPhoto":1743,"socialLinks":1769,"url_path":1770},"Zhuo Feng","Stevens Institute of Technology ","2024-10-18T15:10:14.052Z","203",{"id":1744,"name":1745,"alternativeText":15,"caption":15,"width":1746,"height":1104,"formats":1747,"hash":1765,"ext":18,"mime":19,"size":1766,"url":1767,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1768,"updatedAt":1768},128,"Zhuo Feng_ICCAD.png",754,{"small":1748,"medium":1754,"thumbnail":1760},{"ext":18,"url":1749,"hash":1750,"mime":19,"name":1751,"path":15,"size":1752,"width":1753,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Zhuo_Feng_ICCAD_f12f7d957e.png","small_Zhuo_Feng_ICCAD_f12f7d957e","small_Zhuo Feng_ICCAD.png",359.88,491,{"ext":18,"url":1755,"hash":1756,"mime":19,"name":1757,"path":15,"size":1758,"width":1759,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Zhuo_Feng_ICCAD_f12f7d957e.png","medium_Zhuo_Feng_ICCAD_f12f7d957e","medium_Zhuo Feng_ICCAD.png",699.92,736,{"ext":18,"url":1761,"hash":1762,"mime":19,"name":1763,"path":15,"size":1764,"width":1272,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Zhuo_Feng_ICCAD_f12f7d957e.png","thumbnail_Zhuo_Feng_ICCAD_f12f7d957e","thumbnail_Zhuo Feng_ICCAD.png",46.99,"Zhuo_Feng_ICCAD_f12f7d957e",167.1,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Zhuo_Feng_ICCAD_f12f7d957e.png","2024-10-18T15:10:11.511Z",[],"-162",{"id":316,"name":1772,"committee":15,"position":15,"affiliation":1773,"email":15,"biography":45,"createdAt":1774,"updatedAt":1774,"url_path_id":1775,"contactPhoto":1776,"socialLinks":1791,"url_path":1792},"Zhou Jin","China University of Petroleum-Beijing","2024-10-18T15:09:44.692Z","202",{"id":1777,"name":1778,"alternativeText":15,"caption":15,"width":1779,"height":1780,"formats":1781,"hash":1787,"ext":18,"mime":19,"size":1788,"url":1789,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1790,"updatedAt":1790},127,"Zhou Jin_ICCAD.png",394,450,{"thumbnail":1782},{"ext":18,"url":1783,"hash":1784,"mime":19,"name":1785,"path":15,"size":1786,"width":1210,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Zhou_Jin_ICCAD_ccae35dd76.png","thumbnail_Zhou_Jin_ICCAD_ccae35dd76","thumbnail_Zhou Jin_ICCAD.png",35.2,"Zhou_Jin_ICCAD_ccae35dd76",73.93,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Zhou_Jin_ICCAD_ccae35dd76.png","2024-10-18T15:09:42.568Z",[],"-161",{"id":247,"name":1794,"committee":15,"position":15,"affiliation":1795,"email":15,"biography":1796,"createdAt":1797,"updatedAt":1797,"url_path_id":1798,"contactPhoto":1799,"socialLinks":1815,"url_path":1816},"Sheldon Tan","University of California at Riverside, USA","\u003Cp style=\"text-align:justify;\">Dr. Sheldon Tan is a Professor in the Department of Electrical Engineering, University of California,  Riverside, CA. He is the Associate Director of Compute Engineering Program (CEN) and cooperative faculty  member in the Department of Computer Science and Engineering at UCR. Dr. Sheldon Tan received his B.S.  and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995,  respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa  City, in 1999. He is a visiting professor of Kyoto University as a JSPS Fellow since Dec. 2017. His research  interests include machine and deep learning for VLSI reliability modeling and optimization at circuit and  system levels, machine learning for circuit and thermal simulation, thermal modeling, optimization and  dynamic thermal management for many-core processors. He has published more than 340 technical papers and  has co-authored 6 books on those areas. Dr. Tan received NSF CAREER Award in 2004. He also received  Best Paper Awards from ICSICT'18, ASICON’17, ICCD'07, DAC’09. He also received ASPDAC Prolific  Author Award in 2020. He also received the Honorable Mention Best Paper Award from SMACD’18. He was  a Visiting Professor of Kyoto University as a JSPS Fellow from Dec. 2017 to Jan. 2018. He also served CEDA Distinguished Lecturer for 2022-2023. He has served as TPC Chair for ASPDAC 2021, and the TPC  Vice Chair for ASPDAC 2020. He is serving or served as Editor in Chief for Elsevier’s Integration, the VLSI  Journal, the Associate Editor for three journals: IEEE Transaction on VLSI Systems (TVLSI), ACM  Transaction on Design Automation of Electronic Systems (TODAES) and Elsevier’s Microelectronics  Reliability.\u003C/p>","2024-07-11T19:44:08.547Z","90",{"id":335,"name":1800,"alternativeText":15,"caption":15,"width":1801,"height":1802,"formats":1803,"hash":1810,"ext":760,"mime":763,"size":1811,"url":1812,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1813,"updatedAt":1814},"Sheldon Tan.jpg",317,310,{"thumbnail":1804},{"ext":760,"url":1805,"hash":1806,"mime":763,"name":1807,"path":15,"size":1808,"width":1809,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Sheldon_Tan_e67f02e8f6.jpg","thumbnail_Sheldon_Tan_e67f02e8f6","thumbnail_Sheldon Tan.jpg",5.78,160,"Sheldon_Tan_e67f02e8f6",20.06,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Sheldon_Tan_e67f02e8f6.jpg","2024-07-11T19:43:46.494Z","2024-07-11T19:44:07.442Z",[],"-65","-64",{"data":1819,"meta":1820},{"id":247,"heading":242,"createdAt":248,"updatedAt":249,"publishedAt":250,"url_path_id":251,"url_path":254,"contentType":79},{},1778851353037]