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style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.utdallas.edu/postings/27382\">\u003Cspan style=\"color:#1155cc;\">\u003Cu>Assistant and Associate Professor in Electrical and Computer Engineering\u003C/u>\u003C/span>\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:25.910Z","2024-10-26T20:57:21.210Z","2024-10-21T16:22:27.674Z","205",{"id":1144,"name":1145,"alternativeText":15,"caption":15,"width":1146,"height":1147,"formats":1148,"hash":1166,"ext":18,"mime":19,"size":1167,"url":1168,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1169,"updatedAt":1169},134,"monogram-emblem-border-880-1.png",880,587,{"small":1149,"medium":1155,"thumbnail":1160},{"ext":18,"url":1150,"hash":1151,"mime":19,"name":1152,"path":15,"size":1153,"width":648,"height":1154},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_monogram_emblem_border_880_1_8faf9d88be.png","small_monogram_emblem_border_880_1_8faf9d88be","small_monogram-emblem-border-880-1.png",22.25,334,{"ext":18,"url":1156,"hash":1157,"mime":19,"name":1158,"path":15,"size":1159,"width":655,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_monogram_emblem_border_880_1_8faf9d88be.png","medium_monogram_emblem_border_880_1_8faf9d88be","medium_monogram-emblem-border-880-1.png",35.91,{"ext":18,"url":1161,"hash":1162,"mime":19,"name":1163,"path":15,"size":1164,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_monogram_emblem_border_880_1_8faf9d88be.png","thumbnail_monogram_emblem_border_880_1_8faf9d88be","thumbnail_monogram-emblem-border-880-1.png",9.35,234,"monogram_emblem_border_880_1_8faf9d88be",7.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/monogram_emblem_border_880_1_8faf9d88be.png","2024-10-21T16:21:43.033Z",{"id":1171,"variation":595,"button":1172},61,[1173],{"id":212,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1174,"newWindow":8,"downloadable":15,"shape":15},"https://www.utdallas.edu/","-164",{"id":206,"name":1177,"description":1178,"createdAt":1179,"updatedAt":1180,"publishedAt":1181,"url_path_id":1182,"logo":1183,"website":1197,"url_path":1202},"Peking University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://drive.google.com/file/d/1Kh6kLqgXyZ-yHFcFpN0LtNoZA0l3s-bK/view?usp=drive_link\">Multiple tenure-track faculty positions\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:51.218Z","2024-10-26T20:55:41.318Z","2024-10-21T16:22:53.136Z","206",{"id":649,"name":1184,"alternativeText":15,"caption":15,"width":1185,"height":1102,"formats":1186,"hash":1193,"ext":18,"mime":19,"size":1194,"url":1195,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1196,"updatedAt":1196},"images (3).png",391,{"thumbnail":1187},{"ext":18,"url":1188,"hash":1189,"mime":19,"name":1190,"path":15,"size":1191,"width":589,"height":1192},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_3_68cbc0fd43.png","thumbnail_images_3_68cbc0fd43","thumbnail_images (3).png",17.77,81,"images_3_68cbc0fd43",7.83,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_3_68cbc0fd43.png","2024-10-21T16:21:42.687Z",{"id":1198,"variation":595,"button":1199},62,[1200],{"id":894,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1201,"newWindow":8,"downloadable":15,"shape":15},"https://english.pku.edu.cn/","-165",{"id":160,"name":1204,"description":45,"createdAt":1205,"updatedAt":1206,"publishedAt":1207,"url_path_id":1208,"logo":1209,"website":1231,"url_path":1235},"Chinese University of Hong Kong","2024-10-21T16:23:31.393Z","2024-10-21T16:25:07.701Z","2024-10-21T16:25:07.690Z","207",{"id":1210,"name":1211,"alternativeText":15,"caption":15,"width":1212,"height":1213,"formats":1214,"hash":1227,"ext":18,"mime":19,"size":1228,"url":1229,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1230,"updatedAt":1230},137,"cuhk_logo_2x.png",556,100,{"small":1215,"thumbnail":1221},{"ext":18,"url":1216,"hash":1217,"mime":19,"name":1218,"path":15,"size":1219,"width":648,"height":1220},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_cuhk_logo_2x_2674588b4f.png","small_cuhk_logo_2x_2674588b4f","small_cuhk_logo_2x.png",33.47,90,{"ext":18,"url":1222,"hash":1223,"mime":19,"name":1224,"path":15,"size":1225,"width":589,"height":1226},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_cuhk_logo_2x_2674588b4f.png","thumbnail_cuhk_logo_2x_2674588b4f","thumbnail_cuhk_logo_2x.png",11.33,44,"cuhk_logo_2x_2674588b4f",8.47,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/cuhk_logo_2x_2674588b4f.png","2024-10-21T16:25:04.093Z",{"id":946,"variation":595,"button":1232},[1233],{"id":335,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1234,"newWindow":8,"downloadable":15,"shape":15},"https://www.cuhk.edu.hk/","-166",{"id":310,"name":1237,"description":1238,"createdAt":1239,"updatedAt":1240,"publishedAt":1241,"url_path_id":1242,"logo":1243,"website":1276,"url_path":1280},"California State University, Long Beach","\u003Cp>Openings:\u003C/p>\u003Cp>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://careers.pageuppeople.com/873/lb/en-us/job/543010/assistant-professor-of-computer-science__;!!IKRxdwAv5BmarQ!eQj8K4F3IfjWIwE6lI2-CE4VMHwlbceaBpx6Qm-22ksIX6ZjXv3PrCSF51VgT13ifmtvdqiqtUzmU1Zx7gIuBOf2bWY$\">Assistant Professor of Computer Science\u003C/a>\u003C/p>","2024-10-21T16:25:34.926Z","2024-10-27T19:26:45.135Z","2024-10-21T16:25:37.001Z","208",{"id":1244,"name":1245,"alternativeText":15,"caption":15,"width":1246,"height":1247,"formats":1248,"hash":1273,"ext":18,"mime":19,"size":81,"url":1274,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1275,"updatedAt":1275},136,"49e1116896ee3dd71dd426fcd25cc16b.png",1280,800,{"large":1249,"small":1255,"medium":1261,"thumbnail":1267},{"ext":18,"url":1250,"hash":1251,"mime":19,"name":1252,"path":15,"size":1253,"width":640,"height":1254},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","large_49e1116896ee3dd71dd426fcd25cc16b.png",52.7,625,{"ext":18,"url":1256,"hash":1257,"mime":19,"name":1258,"path":15,"size":1259,"width":648,"height":1260},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","small_49e1116896ee3dd71dd426fcd25cc16b.png",23.09,313,{"ext":18,"url":1262,"hash":1263,"mime":19,"name":1264,"path":15,"size":1265,"width":655,"height":1266},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","medium_49e1116896ee3dd71dd426fcd25cc16b.png",37.06,469,{"ext":18,"url":1268,"hash":1269,"mime":19,"name":1270,"path":15,"size":1271,"width":589,"height":1272},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","thumbnail_49e1116896ee3dd71dd426fcd25cc16b.png",10.13,153,"49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","2024-10-21T16:21:43.178Z",{"id":396,"variation":595,"button":1277},[1278],{"id":316,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1279,"newWindow":8,"downloadable":15,"shape":15},"https://www.csulb.edu/","-167",{"id":227,"name":1282,"description":1283,"createdAt":1284,"updatedAt":1285,"publishedAt":1286,"url_path_id":1287,"logo":1288,"website":1320,"url_path":1325},"NVIDIA","\u003Cp>Openings:\u003C/p>\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/details/Research-Scientist--Design-Automation---New-College-Grad-2025_JR1989394-1?q=JR1989394\">Research scientist\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/PhD-Research-Intern--Robotics-and-or-Autonomous-Vehicles---2025_JR1989940-1?q=JR1989940+PhD+Research+Intern,+Robotics+and/or+Autonomous+Vehicles+-+2025\">Internship link\u003C/a>\u003C/li>\u003C/ul>","2024-10-21T16:26:10.208Z","2024-10-28T21:11:00.165Z","2024-10-21T16:26:12.361Z","209",{"id":1289,"name":1290,"alternativeText":15,"caption":15,"width":1291,"height":1292,"formats":1293,"hash":1316,"ext":18,"mime":19,"size":1317,"url":1318,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1319,"updatedAt":1319},135,"nvidia-logo-horz.png",1070,601,{"large":1294,"small":1300,"medium":1305,"thumbnail":1311},{"ext":18,"url":1295,"hash":1296,"mime":19,"name":1297,"path":15,"size":1298,"width":640,"height":1299},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_nvidia_logo_horz_e2054e7730.png","large_nvidia_logo_horz_e2054e7730","large_nvidia-logo-horz.png",39.87,562,{"ext":18,"url":1301,"hash":1302,"mime":19,"name":1303,"path":15,"size":1304,"width":648,"height":1034},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_nvidia_logo_horz_e2054e7730.png","small_nvidia_logo_horz_e2054e7730","small_nvidia-logo-horz.png",14.82,{"ext":18,"url":1306,"hash":1307,"mime":19,"name":1308,"path":15,"size":1309,"width":655,"height":1310},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_nvidia_logo_horz_e2054e7730.png","medium_nvidia_logo_horz_e2054e7730","medium_nvidia-logo-horz.png",25.1,421,{"ext":18,"url":1312,"hash":1313,"mime":19,"name":1314,"path":15,"size":1315,"width":589,"height":1046},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_nvidia_logo_horz_e2054e7730.png","thumbnail_nvidia_logo_horz_e2054e7730","thumbnail_nvidia-logo-horz.png",6.41,"nvidia_logo_horz_e2054e7730",8.64,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/nvidia_logo_horz_e2054e7730.png","2024-10-21T16:21:43.111Z",{"id":415,"variation":595,"button":1321},[1322],{"id":1323,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1324,"newWindow":8,"downloadable":15,"shape":15},73,"https://www.nvidia.com/en-us/","-168",{"id":247,"name":1327,"description":1328,"createdAt":1329,"updatedAt":1330,"publishedAt":1331,"url_path_id":1332,"logo":1333,"website":1353,"url_path":1358},"Arizona State University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://apply.interfolio.com/156770\">Professor (All Ranks) in Microelectronics\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:27:22.029Z","2024-10-26T20:56:24.414Z","2024-10-21T16:27:23.897Z","210",{"id":1334,"name":1335,"alternativeText":15,"caption":15,"width":1336,"height":1337,"formats":1338,"hash":1349,"ext":18,"mime":19,"size":1350,"url":1351,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1352,"updatedAt":1352},130,"images (4).png",512,98,{"small":1339,"thumbnail":1344},{"ext":18,"url":1340,"hash":1341,"mime":19,"name":1342,"path":15,"size":1343,"width":648,"height":766},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_images_4_722bb37608.png","small_images_4_722bb37608","small_images (4).png",33.41,{"ext":18,"url":1345,"hash":1346,"mime":19,"name":1347,"path":15,"size":1348,"width":589,"height":539},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_4_722bb37608.png","thumbnail_images_4_722bb37608","thumbnail_images (4).png",13.53,"images_4_722bb37608",6.12,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_4_722bb37608.png","2024-10-21T16:21:42.665Z",{"id":1055,"variation":595,"button":1354},[1355],{"id":1356,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1357,"newWindow":15,"downloadable":15,"shape":15},74,"https://www.asu.edu/","-169",{"id":509,"name":1360,"description":1361,"createdAt":1362,"updatedAt":1363,"publishedAt":1364,"url_path_id":1365,"logo":1366,"website":1386,"url_path":1390},"University of Wisconsin","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.wisc.edu/jobs/professor-open-rank-in-electrical-computer-engineering-ai-for-chip-design-madison-wisconsin-united-states\">Professor (open rank) in Electrical & Computer Engineering - AI for Chip Design\u003C/a>\u003C/li>\u003C/ol>\u003Cp> \u003C/p>\u003Cp> \u003C/p>","2024-10-21T16:28:02.562Z","2024-10-26T20:56:56.929Z","2024-10-21T16:28:04.775Z","211",{"id":1367,"name":1368,"alternativeText":15,"caption":15,"width":1369,"height":1370,"formats":1371,"hash":1383,"ext":18,"mime":19,"size":180,"url":1384,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1385,"updatedAt":1385},132,"vert-w-crest-logo-web-digital-color.png",600,400,{"small":1372,"thumbnail":1378},{"ext":18,"url":1373,"hash":1374,"mime":19,"name":1375,"path":15,"size":1376,"width":648,"height":1377},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_vert_w_crest_logo_web_digital_color_beb0805fb0.png","small_vert_w_crest_logo_web_digital_color_beb0805fb0","small_vert-w-crest-logo-web-digital-color.png",62.38,333,{"ext":18,"url":1379,"hash":1380,"mime":19,"name":1381,"path":15,"size":1382,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0.png","thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0","thumbnail_vert-w-crest-logo-web-digital-color.png",20.47,"vert_w_crest_logo_web_digital_color_beb0805fb0","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/vert_w_crest_logo_web_digital_color_beb0805fb0.png","2024-10-21T16:21:42.813Z",{"id":520,"variation":595,"button":1387},[1388],{"id":233,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1389,"newWindow":8,"downloadable":15,"shape":15},"https://www.wisc.edu/","-170",{"id":200,"name":1392,"description":45,"createdAt":1393,"updatedAt":1394,"publishedAt":1395,"url_path_id":1396,"logo":1397,"website":1425,"url_path":1429},"Villanova University","2024-10-26T11:20:53.250Z","2024-10-26T11:20:55.579Z","2024-10-26T11:20:55.572Z","212",{"id":1046,"name":1398,"alternativeText":15,"caption":15,"width":1246,"height":1399,"formats":1400,"hash":1421,"ext":760,"mime":763,"size":1422,"url":1423,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1424,"updatedAt":1424},"image_1579638630.no.size.img.jpg",960,{"large":1401,"small":1406,"medium":1411,"thumbnail":1416},{"ext":760,"url":1402,"hash":1403,"mime":763,"name":1404,"path":15,"size":1405,"width":640,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_image_1579638630_no_size_img_0c4aefb873.jpg","large_image_1579638630_no_size_img_0c4aefb873","large_image_1579638630.no.size.img.jpg",34.67,{"ext":760,"url":1407,"hash":1408,"mime":763,"name":1409,"path":15,"size":1410,"width":648,"height":1079},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_image_1579638630_no_size_img_0c4aefb873.jpg","small_image_1579638630_no_size_img_0c4aefb873","small_image_1579638630.no.size.img.jpg",13.1,{"ext":760,"url":1412,"hash":1413,"mime":763,"name":1414,"path":15,"size":1415,"width":655,"height":1028},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_image_1579638630_no_size_img_0c4aefb873.jpg","medium_image_1579638630_no_size_img_0c4aefb873","medium_image_1579638630.no.size.img.jpg",22.85,{"ext":760,"url":1417,"hash":1418,"mime":763,"name":1419,"path":15,"size":1420,"width":621,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_image_1579638630_no_size_img_0c4aefb873.jpg","thumbnail_image_1579638630_no_size_img_0c4aefb873","thumbnail_image_1579638630.no.size.img.jpg",3.51,"image_1579638630_no_size_img_0c4aefb873",49.04,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/image_1579638630_no_size_img_0c4aefb873.jpg","2024-10-26T11:20:33.114Z",{"id":1133,"variation":595,"button":1426},[1427],{"id":16,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1428,"newWindow":15,"downloadable":15,"shape":15},"https://www1.villanova.edu/university.html","-171",{"id":324,"name":1431,"description":45,"createdAt":1432,"updatedAt":1433,"publishedAt":1434,"url_path_id":1435,"logo":1436,"website":1450,"url_path":1455},"Syracuse University","2024-10-26T18:34:30.431Z","2024-10-26T18:35:05.768Z","2024-10-26T18:35:05.761Z","213",{"id":1437,"name":1438,"alternativeText":15,"caption":15,"width":1439,"height":649,"formats":1440,"hash":1446,"ext":18,"mime":19,"size":1447,"url":1448,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1449,"updatedAt":1449},139,"images (5).png",384,{"thumbnail":1441},{"ext":18,"url":1442,"hash":1443,"mime":19,"name":1444,"path":15,"size":1445,"width":589,"height":582},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_5_292bd7738d.png","thumbnail_images_5_292bd7738d","thumbnail_images (5).png",12.99,"images_5_292bd7738d",4.92,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_5_292bd7738d.png","2024-10-26T18:34:09.860Z",{"id":212,"variation":595,"button":1451},[1452],{"id":1453,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1454,"newWindow":8,"downloadable":15,"shape":15},77,"https://www.syracuse.edu/","-172",{"pagination":1457},{"page":5,"pageSize":324,"pageCount":27,"total":102},{"id":261,"heading":1459,"pageHeader":1460,"sections":1462},"Towards Democratized and Reproducible AI for EDA Research: Open Datasets and Benchmarks in Various Aspects",{"id":261,"description":1461,"showPageHeader":8,"backgroundColor":49,"image":15}," ",[1463],{"id":127,"__component":1464,"componentVariation":1465,"contactsVariation":1466,"styles":15,"header":1467,"sessionsGroup":1470},"content.sessions","Sessions Base","Card Contact Full",{"id":102,"heading":15,"prose":1468,"lead":15,"eyebrow":15,"badge":15,"componentVariation":1469,"containerWidth":15,"image":15},"\u003Cp style=\"text-align:justify;\">Artificial intelligence (AI) techniques have demonstrated remark able effectiveness in electronic design automation (EDA) and agile IC design. For such data-driven technology, the access to high quality, diverse, and representative circuit data is essential for both ML model development and evaluation. However, the lack of circuit data remains a long-standing and primary technical bottleneck. First, the lack of open datasets raises a high barrier to the devel opment of AI for EDA solutions. For ML model training, the label collection process can be highly time-consuming and resource demanding. Also, limited open-source circuit designs may not pro vide sufficient diversity in training, limiting the ML model perfor mance. Second, the lack of open benchmarks makes fair compar isons among different AI for EDA solutions highly challenging. It is difficult for truly outstanding AI solutions to stand out. \u003C/p>\u003Cp style=\"text-align:justify;\">Our special session (SS) delves into this long-lasting circuit data availability challenge by presenting four open-source works from different perspectives. Topics in our SS include 1) an RTL-to-GDS digital dataset and benchmark, 2) an analog circuit synthesis bench mark, 3) both dataset and benchmark about LLM-aided IC design, and 4) AI-assisted circuit data generation techniques and corre sponding datasets. They cover not only both digital and analog design, but also emerging techniques such as LLM-aided design and AI-generated circuit datasets. By releasing four latest explo rations to the public, we hope to contribute to more democratized and reproducible AI for EDA techniques. Specifically, open datasets will allow every researcher to train their AI solutions without an EDA license, and open benchmarks with a leaderboard will facilitate fair comparisons and encourage replications of AI solutions.\u003C/p>","Heading Center",[1471],{"id":127,"groupTitle":15,"sessions":1472},[1473,1505,1533,1566],{"id":477,"session":1474},{"id":477,"title":1475,"teaser":1476,"body":45,"createdAt":1477,"updatedAt":1478,"publishedAt":1479,"url_path_id":1480,"contacts":1481,"url_path":1504},"Dataset and Benchmark for Digital Design","\u003Cp style=\"text-align:justify;\">The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention. Despite the requirement for extensive datasets to build effective ML models, most studies are limited to smaller, internally generated datasets due to the lack of comprehensive public resources. In response, we introduce EDALearn, a holistic, open-source dataset as well as benchmark suite specifically for ML tasks in EDA. It presents an end-to-end flow from synthesis to physical implementation, en riching data collection across various stages. It fosters reproducibil ity and promotes research into ML transferability across different technology nodes. Accommodating a wide range of VLSI design instances and sizes, our dataset and benchmark aptly represent the complexity of contemporary VLSI designs. Additionally, we pro vide an in-depth data analysis, enabling users to fully comprehend the attributes and distribution of our data, which is essential for creating efficient ML models. Our contributions aim to encourage further advances in the ML-EDA domain.\u003C/p>","2024-07-12T14:07:57.467Z","2024-07-12T14:08:00.047Z","2024-07-12T14:08:00.039Z","166",[1482],{"id":855,"name":1483,"committee":15,"position":15,"affiliation":1484,"email":15,"biography":1485,"createdAt":1486,"updatedAt":1486,"url_path_id":1487,"contactPhoto":1488,"socialLinks":1502,"url_path":1503},"Hai (Helen) Li","Duke University, USA","\u003Cp style=\"text-align:justify;\">Hai (Helen) Li (Fellow of ACM and IEEE) received the Ph.D. degree from Purdue University, in 2004. She is currently the Clare Boothe Luce Professor and the Chair of the Electrical and Computer Engineering Department, Duke University. Her cur rent research interests include neuromorphic circuits and systems for brain-inspired computing, machine learning acceleration and trustworthy AI, conventional and emerging memory design and architecture, and software and hardware codesign. She was a recip ient of the NSF Career Award (2012), DARPA Young Faculty Award (2013), TUM-IAS Hans Fischer Fellowship from Germany (2017), and ELATE Fellowship (2020). She received nine best paper awards and additional nine best paper nominations from international con ferences. She is a Distinguished Lecturer of the IEEE CAS Society (2018–2019) and a Distinguished Speaker of ACM (2017–2020). \u003C/p>","2024-07-12T13:58:17.752Z","162",{"id":1489,"name":1490,"alternativeText":15,"caption":15,"width":1491,"height":1491,"formats":1492,"hash":1498,"ext":760,"mime":763,"size":1499,"url":1500,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1501,"updatedAt":1501},102,"Hai (Helen) Li.jpg",200,{"thumbnail":1493},{"ext":760,"url":1494,"hash":1495,"mime":763,"name":1496,"path":15,"size":1497,"width":622,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Hai_Helen_Li_5f22ab81a5.jpg","thumbnail_Hai_Helen_Li_5f22ab81a5","thumbnail_Hai (Helen) Li.jpg",5.29,"Hai_Helen_Li_5f22ab81a5",7.19,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Hai_Helen_Li_5f22ab81a5.jpg","2024-07-12T13:58:14.333Z",[],"-128","-132",{"id":192,"session":1506},{"id":192,"title":1507,"teaser":1508,"body":45,"createdAt":1509,"updatedAt":1510,"publishedAt":1511,"url_path_id":1512,"contacts":1513,"url_path":1532},"Benchmark for Analog Design","\u003Cp style=\"text-align:justify;\">Recent advancements in machine learning (ML) for au tomating analog circuit synthesis have been significant, yet chal lenges remain. A critical gap is the lack of a standardized eval uation framework, compounded by diverse process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and validation of algo rithms. To address these shortcomings, we introduced ACOB, an open-source benchmark suite designed to provide fair and compre hensive evaluations. ACOB includes 30 circuit topologies across five categories—sensing elements, voltage references, oscillators, amplifiers, and phase-locked loops. It supports several technol ogy nodes for both academic and commercial applications and is compatible with commercial simulators like Cadence Spectre and Synopsys HSPICE, as well as the open-source simulator Xyce. This suite not only standardizes the assessment of ML algorithms in analog circuit synthesis but also promotes reproducibility with its open datasets and detailed benchmark specifications. ACOB’s user-friendly design ensures that researchers can easily adopt it for robust, transparent comparisons of state-of-the-art methods, and furthermore, it exposes researchers to real-world problems in industrial design cycles, enhancing the relevance and impact of their work in practical settings. Additionally, we have provided a comprehensive comparison study of different representative meth ods of analog sizing on ACOB, showcasing the capabilities and advantages of various approaches. \u003C/p>","2024-07-12T14:08:51.037Z","2024-07-12T14:08:52.528Z","2024-07-12T14:08:52.523Z","167",[1514],{"id":823,"name":1515,"committee":15,"position":15,"affiliation":1516,"email":15,"biography":1517,"createdAt":1518,"updatedAt":1518,"url_path_id":1519,"contactPhoto":1520,"socialLinks":1530,"url_path":1531},"Xuan Zeng","Fudan University, China","\u003Cp style=\"text-align:justify;\">Xuan Zeng (Senior Member, IEEE) received the B.S. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She is currently a Full Professor with the Microelectronics Department, Fudan University, where she served as the Director of the State Key Laboratory of Application Specific Integrated Circuits (ASIC) and Systems from 2008 to 2012. Her current research interests include analog circuit modeling and synthesis, design for manufacturability, high-speed interconnect analysis and optimization, and circuit simulation. She received the Changjiang Distinguished Professor with the Ministry of Education Department of China in 2014, the Chinese National Science Funds for Distinguished Young Scientists in 2011, the First Class of Natural Science Prize of Shanghai in 2012, the 10th For Women in Science Award in China in 2013, and the Shanghai Mu nicipal Natural Science Peony Award in 2014.\u003C/p>","2024-07-12T14:00:21.037Z","163",{"id":1521,"name":1522,"alternativeText":15,"caption":15,"width":1523,"height":1144,"formats":1524,"hash":1525,"ext":760,"mime":763,"size":1526,"url":1527,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1528,"updatedAt":1529},103,"Xuan Zeng.jpg",149,{},"Xuan_Zeng_ee09c853d9",3.73,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Xuan_Zeng_ee09c853d9.jpg","2024-07-12T14:00:03.247Z","2024-07-12T14:00:19.353Z",[],"-129","-133",{"id":556,"session":1534},{"id":556,"title":1535,"teaser":1536,"body":45,"createdAt":1537,"updatedAt":1538,"publishedAt":1539,"url_path_id":1540,"contacts":1541,"url_path":1565},"Dataset and Benchmark for Llm-Assisted Design","\u003Cp style=\"text-align:justify;\">The automated generation of design RTL based on large language model (LLM) and natural language instructions has demon strated great potential in agile design recently. However, the lack of datasets and benchmarks prevents the development and fair evalu ation of LLM solutions. This work highlights our latest advances in open datasets and benchmarks from three perspectives. (1) RTL Coder (latest update), an automated data generation flow, which has generated an open-source dataset with 30 thousand RTL gener ation samples. Open-source LLMs fine-tuned on this dataset prove to outperform the commercial GPT-3.5. (2) RTLLM 2.0, an updated benchmark for HDL generation. The benchmark is augmented to 50 hand-crafted designs. Each design provides the design description at different granularities, test cases, and a correct RTL code. (3) As sertLLM, an open-source benchmark assessing the LLM’s assertion generation capabilities. The benchmark includes 20 designs, each providing specification, signal definition, and correct RTL code. These three studies are integrated into one framework, providing off-the-shelf support for the development and evaluation of LLMs for RTL code generation and verification.\u003C/p>","2024-07-12T14:10:37.310Z","2024-07-12T14:10:40.800Z","2024-07-12T14:10:40.795Z","168",[1542],{"id":783,"name":1543,"committee":15,"position":15,"affiliation":1544,"email":15,"biography":1545,"createdAt":1546,"updatedAt":1546,"url_path_id":1547,"contactPhoto":1548,"socialLinks":1563,"url_path":1564},"Zhiyao Xie","HKUST, China","\u003Cp style=\"text-align:justify;\">Zhiyao Xie is an Assistant Professor of the Depart ment of Electronic and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST). Zhiyao re ceived his Ph.D. degree from Duke University in 2022 and B.Eng. from City University of Hong Kong in 2017. His research interests include machine learning algorithms for EDA and VLSI design. He has received multiple prestigious awards, including the IEEE/ACM MICRO 2021 Best Paper Award, ACM SIGDA SRF Best Research Poster Award 2022, ASP-DAC 2023 Best Paper Award, ACM Out standing Dissertation Award in EDA 2023, EDAA Outstanding Dissertation Award 2023, and the 2023 Early Career Award from Hong Kong Research Grants Council (RGC).\u003C/p>","2024-07-12T14:04:27.751Z","164",{"id":1124,"name":1549,"alternativeText":15,"caption":15,"width":1550,"height":1551,"formats":1552,"hash":1559,"ext":760,"mime":763,"size":1560,"url":1561,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1562,"updatedAt":1562},"Zhiyao Xie.jpg",260,354,{"thumbnail":1553},{"ext":760,"url":1554,"hash":1555,"mime":763,"name":1556,"path":15,"size":1557,"width":1558,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Zhiyao_Xie_da7bb8583d.jpg","thumbnail_Zhiyao_Xie_da7bb8583d","thumbnail_Zhiyao Xie.jpg",3.63,115,"Zhiyao_Xie_da7bb8583d",12.45,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Zhiyao_Xie_da7bb8583d.jpg","2024-07-12T14:04:24.204Z",[],"-130","-134",{"id":1567,"session":1568},51,{"id":1567,"title":1569,"teaser":1570,"body":45,"createdAt":1571,"updatedAt":1572,"publishedAt":1573,"url_path_id":1574,"contacts":1575,"url_path":1651},"AI-Assisted Dataset Generation","\u003Cp style=\"text-align:justify;\">The EDA community has recently begun recognizing the potential of generative artificial intelligence (AI) in chip design. However, its full potential is not fully exploited due to the limited availability of publicly accessible datasets crucial for advancing research in EDA. This paper highlights the dual role of generative AI; in particular, it showcases (i) BeGAN, the use of a generative AI strategy to create thousands of realistic benchmarks for power grid synthesis and analysis to advance power-related research, and (ii) EDA Corpus—an expert-curated and generative AI-enhanced dataset to serve research and development of EDA tool assistants. These two case studies serve to emphasize the ability of generative methods to both create and utilize datasets to advance research and lower the barriers to entry in EDA.\u003C/p>","2024-07-12T14:11:26.099Z","2024-07-12T14:11:29.363Z","2024-07-12T14:11:29.357Z","169",[1576,1612],{"id":409,"name":1577,"committee":15,"position":15,"affiliation":1578,"email":15,"biography":1579,"createdAt":1580,"updatedAt":1581,"url_path_id":1582,"contactPhoto":1583,"socialLinks":1610,"url_path":1611},"Sachin Sapatnekar","University of Minnesota, USA","\u003Cp style=\"text-align:justify;\">Sachin S. Sapatnekar received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992.  He was on the faculty at Iowa State University for five years, and since 1997, he has been teaching at the University of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Chair Professorship in ECE. His research is related to developing CAD techniques for the analysis and optimization of circuit performance, currently focused on analog and digital CMOS circuits as well as post-CMOS technologies and novel computational models. He has served as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for the ACM/IEEE Design Automation Conference (DAC), and was lead PI of the ALIGN analog EDA project.  He is a recipient of ten conference Best Paper Awards, two ICCAD Ten Year Retrospective Best Paper Awards, the Semiconductor Research Corporation's Technical Excellence Award, the Semiconductor Industry Association University Research Award, a Fulbright award, and the UMN ECE Penrose Teaching Award. He is a Fellow of the IEEE and the ACM.\u003C/p>","2024-07-08T17:31:49.797Z","2024-09-12T20:36:57.617Z","73",{"id":415,"name":1584,"alternativeText":15,"caption":15,"width":1585,"height":1586,"formats":1587,"hash":1605,"ext":760,"mime":763,"size":1606,"url":1607,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1608,"updatedAt":1609},"Sachin Sapatnekar_1.jpg.jpg",779,815,{"small":1588,"medium":1594,"thumbnail":1600},{"ext":760,"url":1589,"hash":1590,"mime":763,"name":1591,"path":15,"size":1592,"width":1593,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Sachin_Sapatnekar_1_jpg_eca1277b96.jpg","small_Sachin_Sapatnekar_1_jpg_eca1277b96","small_Sachin Sapatnekar_1.jpg.jpg",34.95,478,{"ext":760,"url":1595,"hash":1596,"mime":763,"name":1597,"path":15,"size":1598,"width":1599,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Sachin_Sapatnekar_1_jpg_eca1277b96.jpg","medium_Sachin_Sapatnekar_1_jpg_eca1277b96","medium_Sachin Sapatnekar_1.jpg.jpg",73.25,717,{"ext":760,"url":1601,"hash":1602,"mime":763,"name":1603,"path":15,"size":1604,"width":1523,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Sachin_Sapatnekar_1_jpg_eca1277b96.jpg","thumbnail_Sachin_Sapatnekar_1_jpg_eca1277b96","thumbnail_Sachin Sapatnekar_1.jpg.jpg",4.72,"Sachin_Sapatnekar_1_jpg_eca1277b96",85.31,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Sachin_Sapatnekar_1_jpg_eca1277b96.jpg","2024-07-08T17:31:29.201Z","2024-07-08T17:31:48.381Z",[],"-50",{"id":1613,"name":1614,"committee":15,"position":15,"affiliation":1615,"email":15,"biography":1616,"createdAt":1617,"updatedAt":1617,"url_path_id":1618,"contactPhoto":1619,"socialLinks":1649,"url_path":1650},57,"Vidya A. Chhabria","Arizona State University, USA","\u003Cp style=\"text-align:justify;\">Vidya A. Chhabria is an Assistant Professor at the School of Electrical, Computer, and Energy Engineering at Arizona State University. She received her Ph.D. in Electrical Engineering from the University of Minnesota in 2022. Her research interests are in EDA, including machine learning for chip design, hetero geneous integration, and environmentally sustainable computing. She has received the ICCAD Best Paper Award (2021), the Doctoral Dissertation Fellowship (2021), the Louise T. Dosdall Fellowship (2020), and the Cadence Women in Technology scholarship (2020). \u003C/p>","2024-07-12T14:06:38.482Z","165",{"id":1620,"name":1621,"alternativeText":15,"caption":15,"width":1622,"height":1623,"formats":1624,"hash":1645,"ext":760,"mime":763,"size":1646,"url":1647,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1648,"updatedAt":1648},105,"Vidya A. Chhabria.jpg",2560,1920,{"large":1625,"small":1630,"medium":1635,"thumbnail":1640},{"ext":760,"url":1626,"hash":1627,"mime":763,"name":1628,"path":15,"size":1629,"width":640,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_Vidya_A_Chhabria_b555773d0a.jpg","large_Vidya_A_Chhabria_b555773d0a","large_Vidya A. Chhabria.jpg",95.16,{"ext":760,"url":1631,"hash":1632,"mime":763,"name":1633,"path":15,"size":1634,"width":648,"height":1079},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Vidya_A_Chhabria_b555773d0a.jpg","small_Vidya_A_Chhabria_b555773d0a","small_Vidya A. Chhabria.jpg",23.08,{"ext":760,"url":1636,"hash":1637,"mime":763,"name":1638,"path":15,"size":1639,"width":655,"height":1028},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Vidya_A_Chhabria_b555773d0a.jpg","medium_Vidya_A_Chhabria_b555773d0a","medium_Vidya A. Chhabria.jpg",53.75,{"ext":760,"url":1641,"hash":1642,"mime":763,"name":1643,"path":15,"size":1644,"width":621,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Vidya_A_Chhabria_b555773d0a.jpg","thumbnail_Vidya_A_Chhabria_b555773d0a","thumbnail_Vidya A. Chhabria.jpg",4.86,"Vidya_A_Chhabria_b555773d0a",499.23,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Vidya_A_Chhabria_b555773d0a.jpg","2024-07-12T14:06:35.855Z",[],"-131","-135",{"data":1653,"meta":1659},{"id":261,"heading":1459,"createdAt":1654,"updatedAt":1655,"publishedAt":1656,"url_path_id":1657,"url_path":1658,"contentType":79},"2024-07-12T14:12:44.381Z","2024-07-12T14:15:13.721Z","2024-07-12T14:12:47.634Z","170","/ss7",{},1778851353037]