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style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.utdallas.edu/postings/27382\">\u003Cspan style=\"color:#1155cc;\">\u003Cu>Assistant and Associate Professor in Electrical and Computer Engineering\u003C/u>\u003C/span>\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:25.910Z","2024-10-26T20:57:21.210Z","2024-10-21T16:22:27.674Z","205",{"id":1144,"name":1145,"alternativeText":15,"caption":15,"width":1146,"height":1147,"formats":1148,"hash":1166,"ext":18,"mime":19,"size":1167,"url":1168,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1169,"updatedAt":1169},134,"monogram-emblem-border-880-1.png",880,587,{"small":1149,"medium":1155,"thumbnail":1160},{"ext":18,"url":1150,"hash":1151,"mime":19,"name":1152,"path":15,"size":1153,"width":648,"height":1154},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_monogram_emblem_border_880_1_8faf9d88be.png","small_monogram_emblem_border_880_1_8faf9d88be","small_monogram-emblem-border-880-1.png",22.25,334,{"ext":18,"url":1156,"hash":1157,"mime":19,"name":1158,"path":15,"size":1159,"width":655,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_monogram_emblem_border_880_1_8faf9d88be.png","medium_monogram_emblem_border_880_1_8faf9d88be","medium_monogram-emblem-border-880-1.png",35.91,{"ext":18,"url":1161,"hash":1162,"mime":19,"name":1163,"path":15,"size":1164,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_monogram_emblem_border_880_1_8faf9d88be.png","thumbnail_monogram_emblem_border_880_1_8faf9d88be","thumbnail_monogram-emblem-border-880-1.png",9.35,234,"monogram_emblem_border_880_1_8faf9d88be",7.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/monogram_emblem_border_880_1_8faf9d88be.png","2024-10-21T16:21:43.033Z",{"id":1171,"variation":595,"button":1172},61,[1173],{"id":212,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1174,"newWindow":8,"downloadable":15,"shape":15},"https://www.utdallas.edu/","-164",{"id":206,"name":1177,"description":1178,"createdAt":1179,"updatedAt":1180,"publishedAt":1181,"url_path_id":1182,"logo":1183,"website":1197,"url_path":1202},"Peking University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://drive.google.com/file/d/1Kh6kLqgXyZ-yHFcFpN0LtNoZA0l3s-bK/view?usp=drive_link\">Multiple tenure-track faculty positions\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:22:51.218Z","2024-10-26T20:55:41.318Z","2024-10-21T16:22:53.136Z","206",{"id":649,"name":1184,"alternativeText":15,"caption":15,"width":1185,"height":1102,"formats":1186,"hash":1193,"ext":18,"mime":19,"size":1194,"url":1195,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1196,"updatedAt":1196},"images (3).png",391,{"thumbnail":1187},{"ext":18,"url":1188,"hash":1189,"mime":19,"name":1190,"path":15,"size":1191,"width":589,"height":1192},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_3_68cbc0fd43.png","thumbnail_images_3_68cbc0fd43","thumbnail_images (3).png",17.77,81,"images_3_68cbc0fd43",7.83,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_3_68cbc0fd43.png","2024-10-21T16:21:42.687Z",{"id":1198,"variation":595,"button":1199},62,[1200],{"id":894,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1201,"newWindow":8,"downloadable":15,"shape":15},"https://english.pku.edu.cn/","-165",{"id":160,"name":1204,"description":45,"createdAt":1205,"updatedAt":1206,"publishedAt":1207,"url_path_id":1208,"logo":1209,"website":1231,"url_path":1235},"Chinese University of Hong Kong","2024-10-21T16:23:31.393Z","2024-10-21T16:25:07.701Z","2024-10-21T16:25:07.690Z","207",{"id":1210,"name":1211,"alternativeText":15,"caption":15,"width":1212,"height":1213,"formats":1214,"hash":1227,"ext":18,"mime":19,"size":1228,"url":1229,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1230,"updatedAt":1230},137,"cuhk_logo_2x.png",556,100,{"small":1215,"thumbnail":1221},{"ext":18,"url":1216,"hash":1217,"mime":19,"name":1218,"path":15,"size":1219,"width":648,"height":1220},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_cuhk_logo_2x_2674588b4f.png","small_cuhk_logo_2x_2674588b4f","small_cuhk_logo_2x.png",33.47,90,{"ext":18,"url":1222,"hash":1223,"mime":19,"name":1224,"path":15,"size":1225,"width":589,"height":1226},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_cuhk_logo_2x_2674588b4f.png","thumbnail_cuhk_logo_2x_2674588b4f","thumbnail_cuhk_logo_2x.png",11.33,44,"cuhk_logo_2x_2674588b4f",8.47,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/cuhk_logo_2x_2674588b4f.png","2024-10-21T16:25:04.093Z",{"id":946,"variation":595,"button":1232},[1233],{"id":335,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1234,"newWindow":8,"downloadable":15,"shape":15},"https://www.cuhk.edu.hk/","-166",{"id":310,"name":1237,"description":1238,"createdAt":1239,"updatedAt":1240,"publishedAt":1241,"url_path_id":1242,"logo":1243,"website":1276,"url_path":1280},"California State University, Long Beach","\u003Cp>Openings:\u003C/p>\u003Cp>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://urldefense.com/v3/__https://careers.pageuppeople.com/873/lb/en-us/job/543010/assistant-professor-of-computer-science__;!!IKRxdwAv5BmarQ!eQj8K4F3IfjWIwE6lI2-CE4VMHwlbceaBpx6Qm-22ksIX6ZjXv3PrCSF51VgT13ifmtvdqiqtUzmU1Zx7gIuBOf2bWY$\">Assistant Professor of Computer Science\u003C/a>\u003C/p>","2024-10-21T16:25:34.926Z","2024-10-27T19:26:45.135Z","2024-10-21T16:25:37.001Z","208",{"id":1244,"name":1245,"alternativeText":15,"caption":15,"width":1246,"height":1247,"formats":1248,"hash":1273,"ext":18,"mime":19,"size":81,"url":1274,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1275,"updatedAt":1275},136,"49e1116896ee3dd71dd426fcd25cc16b.png",1280,800,{"large":1249,"small":1255,"medium":1261,"thumbnail":1267},{"ext":18,"url":1250,"hash":1251,"mime":19,"name":1252,"path":15,"size":1253,"width":640,"height":1254},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","large_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","large_49e1116896ee3dd71dd426fcd25cc16b.png",52.7,625,{"ext":18,"url":1256,"hash":1257,"mime":19,"name":1258,"path":15,"size":1259,"width":648,"height":1260},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","small_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","small_49e1116896ee3dd71dd426fcd25cc16b.png",23.09,313,{"ext":18,"url":1262,"hash":1263,"mime":19,"name":1264,"path":15,"size":1265,"width":655,"height":1266},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","medium_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","medium_49e1116896ee3dd71dd426fcd25cc16b.png",37.06,469,{"ext":18,"url":1268,"hash":1269,"mime":19,"name":1270,"path":15,"size":1271,"width":589,"height":1272},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","thumbnail_49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","thumbnail_49e1116896ee3dd71dd426fcd25cc16b.png",10.13,153,"49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/49e1116896ee3dd71dd426fcd25cc16b_10ef1ddb33.png","2024-10-21T16:21:43.178Z",{"id":396,"variation":595,"button":1277},[1278],{"id":316,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1279,"newWindow":8,"downloadable":15,"shape":15},"https://www.csulb.edu/","-167",{"id":227,"name":1282,"description":1283,"createdAt":1284,"updatedAt":1285,"publishedAt":1286,"url_path_id":1287,"logo":1288,"website":1320,"url_path":1325},"NVIDIA","\u003Cp>Openings:\u003C/p>\u003Cul>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/details/Research-Scientist--Design-Automation---New-College-Grad-2025_JR1989394-1?q=JR1989394\">Research scientist\u003C/a>\u003C/li>\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/PhD-Research-Intern--Robotics-and-or-Autonomous-Vehicles---2025_JR1989940-1?q=JR1989940+PhD+Research+Intern,+Robotics+and/or+Autonomous+Vehicles+-+2025\">Internship link\u003C/a>\u003C/li>\u003C/ul>","2024-10-21T16:26:10.208Z","2024-10-28T21:11:00.165Z","2024-10-21T16:26:12.361Z","209",{"id":1289,"name":1290,"alternativeText":15,"caption":15,"width":1291,"height":1292,"formats":1293,"hash":1316,"ext":18,"mime":19,"size":1317,"url":1318,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1319,"updatedAt":1319},135,"nvidia-logo-horz.png",1070,601,{"large":1294,"small":1300,"medium":1305,"thumbnail":1311},{"ext":18,"url":1295,"hash":1296,"mime":19,"name":1297,"path":15,"size":1298,"width":640,"height":1299},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_nvidia_logo_horz_e2054e7730.png","large_nvidia_logo_horz_e2054e7730","large_nvidia-logo-horz.png",39.87,562,{"ext":18,"url":1301,"hash":1302,"mime":19,"name":1303,"path":15,"size":1304,"width":648,"height":1034},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_nvidia_logo_horz_e2054e7730.png","small_nvidia_logo_horz_e2054e7730","small_nvidia-logo-horz.png",14.82,{"ext":18,"url":1306,"hash":1307,"mime":19,"name":1308,"path":15,"size":1309,"width":655,"height":1310},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_nvidia_logo_horz_e2054e7730.png","medium_nvidia_logo_horz_e2054e7730","medium_nvidia-logo-horz.png",25.1,421,{"ext":18,"url":1312,"hash":1313,"mime":19,"name":1314,"path":15,"size":1315,"width":589,"height":1046},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_nvidia_logo_horz_e2054e7730.png","thumbnail_nvidia_logo_horz_e2054e7730","thumbnail_nvidia-logo-horz.png",6.41,"nvidia_logo_horz_e2054e7730",8.64,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/nvidia_logo_horz_e2054e7730.png","2024-10-21T16:21:43.111Z",{"id":415,"variation":595,"button":1321},[1322],{"id":1323,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1324,"newWindow":8,"downloadable":15,"shape":15},73,"https://www.nvidia.com/en-us/","-168",{"id":247,"name":1327,"description":1328,"createdAt":1329,"updatedAt":1330,"publishedAt":1331,"url_path_id":1332,"logo":1333,"website":1353,"url_path":1358},"Arizona State University","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://apply.interfolio.com/156770\">Professor (All Ranks) in Microelectronics\u003C/a>\u003C/li>\u003C/ol>","2024-10-21T16:27:22.029Z","2024-10-26T20:56:24.414Z","2024-10-21T16:27:23.897Z","210",{"id":1334,"name":1335,"alternativeText":15,"caption":15,"width":1336,"height":1337,"formats":1338,"hash":1349,"ext":18,"mime":19,"size":1350,"url":1351,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1352,"updatedAt":1352},130,"images (4).png",512,98,{"small":1339,"thumbnail":1344},{"ext":18,"url":1340,"hash":1341,"mime":19,"name":1342,"path":15,"size":1343,"width":648,"height":766},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_images_4_722bb37608.png","small_images_4_722bb37608","small_images (4).png",33.41,{"ext":18,"url":1345,"hash":1346,"mime":19,"name":1347,"path":15,"size":1348,"width":589,"height":539},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_4_722bb37608.png","thumbnail_images_4_722bb37608","thumbnail_images (4).png",13.53,"images_4_722bb37608",6.12,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_4_722bb37608.png","2024-10-21T16:21:42.665Z",{"id":1055,"variation":595,"button":1354},[1355],{"id":1356,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1357,"newWindow":15,"downloadable":15,"shape":15},74,"https://www.asu.edu/","-169",{"id":509,"name":1360,"description":1361,"createdAt":1362,"updatedAt":1363,"publishedAt":1364,"url_path_id":1365,"logo":1366,"website":1386,"url_path":1390},"University of Wisconsin","\u003Cp>Openings:\u003C/p>\u003Col style=\"list-style-type:decimal;\">\u003Cli>\u003Ca target=\"_blank\" rel=\"noopener noreferrer\" href=\"https://jobs.wisc.edu/jobs/professor-open-rank-in-electrical-computer-engineering-ai-for-chip-design-madison-wisconsin-united-states\">Professor (open rank) in Electrical & Computer Engineering - AI for Chip Design\u003C/a>\u003C/li>\u003C/ol>\u003Cp> \u003C/p>\u003Cp> \u003C/p>","2024-10-21T16:28:02.562Z","2024-10-26T20:56:56.929Z","2024-10-21T16:28:04.775Z","211",{"id":1367,"name":1368,"alternativeText":15,"caption":15,"width":1369,"height":1370,"formats":1371,"hash":1383,"ext":18,"mime":19,"size":180,"url":1384,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1385,"updatedAt":1385},132,"vert-w-crest-logo-web-digital-color.png",600,400,{"small":1372,"thumbnail":1378},{"ext":18,"url":1373,"hash":1374,"mime":19,"name":1375,"path":15,"size":1376,"width":648,"height":1377},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_vert_w_crest_logo_web_digital_color_beb0805fb0.png","small_vert_w_crest_logo_web_digital_color_beb0805fb0","small_vert-w-crest-logo-web-digital-color.png",62.38,333,{"ext":18,"url":1379,"hash":1380,"mime":19,"name":1381,"path":15,"size":1382,"width":1165,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0.png","thumbnail_vert_w_crest_logo_web_digital_color_beb0805fb0","thumbnail_vert-w-crest-logo-web-digital-color.png",20.47,"vert_w_crest_logo_web_digital_color_beb0805fb0","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/vert_w_crest_logo_web_digital_color_beb0805fb0.png","2024-10-21T16:21:42.813Z",{"id":520,"variation":595,"button":1387},[1388],{"id":233,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1389,"newWindow":8,"downloadable":15,"shape":15},"https://www.wisc.edu/","-170",{"id":200,"name":1392,"description":45,"createdAt":1393,"updatedAt":1394,"publishedAt":1395,"url_path_id":1396,"logo":1397,"website":1425,"url_path":1429},"Villanova University","2024-10-26T11:20:53.250Z","2024-10-26T11:20:55.579Z","2024-10-26T11:20:55.572Z","212",{"id":1046,"name":1398,"alternativeText":15,"caption":15,"width":1246,"height":1399,"formats":1400,"hash":1421,"ext":760,"mime":763,"size":1422,"url":1423,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1424,"updatedAt":1424},"image_1579638630.no.size.img.jpg",960,{"large":1401,"small":1406,"medium":1411,"thumbnail":1416},{"ext":760,"url":1402,"hash":1403,"mime":763,"name":1404,"path":15,"size":1405,"width":640,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/large_image_1579638630_no_size_img_0c4aefb873.jpg","large_image_1579638630_no_size_img_0c4aefb873","large_image_1579638630.no.size.img.jpg",34.67,{"ext":760,"url":1407,"hash":1408,"mime":763,"name":1409,"path":15,"size":1410,"width":648,"height":1079},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_image_1579638630_no_size_img_0c4aefb873.jpg","small_image_1579638630_no_size_img_0c4aefb873","small_image_1579638630.no.size.img.jpg",13.1,{"ext":760,"url":1412,"hash":1413,"mime":763,"name":1414,"path":15,"size":1415,"width":655,"height":1028},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_image_1579638630_no_size_img_0c4aefb873.jpg","medium_image_1579638630_no_size_img_0c4aefb873","medium_image_1579638630.no.size.img.jpg",22.85,{"ext":760,"url":1417,"hash":1418,"mime":763,"name":1419,"path":15,"size":1420,"width":621,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_image_1579638630_no_size_img_0c4aefb873.jpg","thumbnail_image_1579638630_no_size_img_0c4aefb873","thumbnail_image_1579638630.no.size.img.jpg",3.51,"image_1579638630_no_size_img_0c4aefb873",49.04,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/image_1579638630_no_size_img_0c4aefb873.jpg","2024-10-26T11:20:33.114Z",{"id":1133,"variation":595,"button":1426},[1427],{"id":16,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1428,"newWindow":15,"downloadable":15,"shape":15},"https://www1.villanova.edu/university.html","-171",{"id":324,"name":1431,"description":45,"createdAt":1432,"updatedAt":1433,"publishedAt":1434,"url_path_id":1435,"logo":1436,"website":1450,"url_path":1455},"Syracuse University","2024-10-26T18:34:30.431Z","2024-10-26T18:35:05.768Z","2024-10-26T18:35:05.761Z","213",{"id":1437,"name":1438,"alternativeText":15,"caption":15,"width":1439,"height":649,"formats":1440,"hash":1446,"ext":18,"mime":19,"size":1447,"url":1448,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1449,"updatedAt":1449},139,"images (5).png",384,{"thumbnail":1441},{"ext":18,"url":1442,"hash":1443,"mime":19,"name":1444,"path":15,"size":1445,"width":589,"height":582},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_images_5_292bd7738d.png","thumbnail_images_5_292bd7738d","thumbnail_images (5).png",12.99,"images_5_292bd7738d",4.92,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/images_5_292bd7738d.png","2024-10-26T18:34:09.860Z",{"id":212,"variation":595,"button":1451},[1452],{"id":1453,"label":598,"size":599,"color":600,"style":15,"icon":601,"iconPosition":602,"url":1454,"newWindow":8,"downloadable":15,"shape":15},77,"https://www.syracuse.edu/","-172",{"pagination":1457},{"page":5,"pageSize":324,"pageCount":27,"total":102},{"id":324,"heading":1459,"pageHeader":1460,"sections":1462},"AI4HLS: New Frontiers in High-Level Synthesis Augmented with Artificial Intelligence",{"id":324,"description":1461,"showPageHeader":8,"backgroundColor":49,"image":15}," ",[1463],{"id":90,"__component":1464,"componentVariation":1465,"contactsVariation":1466,"styles":15,"header":1467,"sessionsGroup":1470},"content.sessions","Sessions Base","Card Contact Full",{"id":227,"heading":15,"prose":1468,"lead":15,"eyebrow":15,"badge":15,"componentVariation":1469,"containerWidth":15,"image":15},"\u003Cp style=\"text-align:justify;\">Artificial intelligence (AI) and Machine Learning (ML) methods are profoundly changing design automation (DA). All areas of DA are  exploring AI-based approaches to improve the quality result. From system-level design to logic synthesis, placing, and routing, and all physical  layout methods, AI promises to identify optimal solutions while significantly reducing time-to-completion of the search. In this special session, we  specifically discuss the use of AI-enabled methods in High-Level Synthesis (HLS). While generative AI and large language models (LLMs) have the  potential of being revolutionary for HLS, thanks to their ability to generate register transfer-level (RTL) descriptions starting from natural language,  they need to be carefully evaluated when considering quality and verifiability of the resulting design, and the size of the design they can currently  deal with. Additionally, they are not the only potentially disruptive solution, as design space exploration and classical optimization methods in HLS  might greatly benefit from ML. This special session discusses the opportunities and challenges of augmenting HLS with AI, including LLMs,  prediction methods, and novel optimization approaches, and their impacts on the overall agile hardware design automation flow. \u003C/p>","Heading Center",[1471],{"id":90,"groupTitle":15,"sessions":1472},[1473,1519,1564,1601],{"id":247,"session":1474},{"id":247,"title":1475,"teaser":1476,"body":45,"createdAt":1477,"updatedAt":1478,"publishedAt":1479,"url_path_id":1480,"contacts":1481,"url_path":1518},"The Promise and Challenges of Designing Digital Logic though Backpropagation","\u003Cp style=\"text-align:justify;\">Certain hardware functions such as branch predictors or memory prefetchers operate speculatively and therefore (1) don't have an ideal  specification and (2) are tolerant to design and implementation errors. Designing such modules can be represented as supervised learning task,  however, machine learning models typically do not have an efficient hardware implementation. In this work we present an approach for training  and synthesizing area-efficient hardware purely from input-output traces. Next, we extend the data-driven hardware specification problem from  conventional datasets (e.g., branch traces) to synthetic datasets, where we design hardware that matches input-output (but not timing) behavior of  software binaries. We present our language-agnostic high-level synthesis tool and discuss some challenges in training and verifying generated  hardware designs.\u003C/p>","2024-07-12T12:28:46.730Z","2024-07-12T12:36:14.777Z","2024-07-12T12:28:48.376Z","109",[1482],{"id":442,"name":1483,"committee":15,"position":15,"affiliation":1484,"email":15,"biography":1485,"createdAt":1486,"updatedAt":1487,"url_path_id":1488,"contactPhoto":1489,"socialLinks":1516,"url_path":1517},"Mihailo Isakov","BoolSi","\u003Cp style=\"text-align:justify;\">Mihailo Isakov received his PhD in computer engineering from Arizona State University in 2022 on the topic of self-aware adaptive general purpose computing systems. He has since started BoolSi, a venture-funded generative chip design startup. \u003C/p>","2024-07-12T12:30:14.865Z","2024-07-12T12:33:44.427Z","110",{"id":1192,"name":1490,"alternativeText":15,"caption":15,"width":1491,"height":1492,"formats":1493,"hash":1512,"ext":18,"mime":19,"size":1513,"url":1514,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1515,"updatedAt":1515},"Mihailo Isakov.png",866,787,{"small":1494,"medium":1500,"thumbnail":1506},{"ext":18,"url":1495,"hash":1496,"mime":19,"name":1497,"path":15,"size":1498,"width":648,"height":1499},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Mihailo_Isakov_f538b981c0.png","small_Mihailo_Isakov_f538b981c0","small_Mihailo Isakov.png",360.37,454,{"ext":18,"url":1501,"hash":1502,"mime":19,"name":1503,"path":15,"size":1504,"width":655,"height":1505},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Mihailo_Isakov_f538b981c0.png","medium_Mihailo_Isakov_f538b981c0","medium_Mihailo Isakov.png",803.97,682,{"ext":18,"url":1507,"hash":1508,"mime":19,"name":1509,"path":15,"size":1510,"width":1511,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Mihailo_Isakov_f538b981c0.png","thumbnail_Mihailo_Isakov_f538b981c0","thumbnail_Mihailo Isakov.png",45.87,172,"Mihailo_Isakov_f538b981c0",287.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Mihailo_Isakov_f538b981c0.png","2024-07-12T12:30:02.086Z",[],"-82","-81",{"id":509,"session":1520},{"id":509,"title":1521,"teaser":1522,"body":45,"createdAt":1523,"updatedAt":1524,"publishedAt":1525,"url_path_id":1526,"contacts":1527,"url_path":1563},"Extending High-Level Synthesis with AI/ML Methods","\u003Cp style=\"text-align:justify;\">Artificial Intelligence (AI) and Machine Learning (ML) methods provide significant opportunities of improving quality of results when performing high-level synthesis (HLS). For example, they can be used to model and predict metrics of the final design (e.g., area, considering aspects such as interconnect overhead for different device technologies), facilitating exploration when searching for the best design trade-offs. They can also enable identifying hidden correlations across the various phases of the synthesis and the various optimizations performed, identifying the most effective pipelines. Finally, in more general terms, bio-inspired heuristic algorithms can improve the design space exploration for the synthesis process in terms of time and quality of the result. This talk discusses opportunities and challenges to augment HLS with AI/ML using as example flow the SODA Synthesizer, an open-source hardware generation toolchain which includes SODA-OPT, a hardware/software partitioning and pre-optimization tool developed with the MLIR framework, and PandA-Bambu, a state-of-the art HLS tool. SODA interfaces with OpenROAD to provide a complete end-to-end toolchain.\u003C/p>","2024-07-12T12:36:55.970Z","2024-07-12T12:36:57.278Z","2024-07-12T12:36:57.272Z","114",[1528],{"id":423,"name":1529,"committee":15,"position":15,"affiliation":1530,"email":15,"biography":1531,"createdAt":1532,"updatedAt":1532,"url_path_id":1533,"contactPhoto":1534,"socialLinks":1561,"url_path":1562},"Antonino Tumeo","Pacific Northwest National Laboratory, WA, USA","\u003Cp style=\"text-align:justify;\">Dr Antonino Tumeo received an MS degree in Informatic Engineering (2005) and a PhD in Computer Engineering (2009) from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in Pacific Northwest National Laboratory’s (PNNL) High-Performance Computing (HPC) group. He joined PNNL in 2009 as a post-doctoral research associate. Previously, he was a post-doctoral researcher at Politecnico di Milano. His research interests include modeling and simulation of high performance architectures, hardware-software codesign, electronic design automation, high-level synthesis, field-programmable gate arrays (FGPA) prototyping, and general-purpose computing on graphics processing units (GPGPU). Antonino is currently the principal investigator of SODALITE (Software Defined Accelerators from Learning Tools Environment), a project under the Real Time Machine Learning program of the Defense Advanced Research Projects Agency related to the automatic generation of machine learning accelerators, and SO(DA)2 (Software Defined Architectures for Data Analytics), a project under the Data-Model Convergence Initiative. The SO(DA)2 project is related to the development of a toolchain for efficient acceleration of emerging HPC applications (integrating scientific simulation with machine learning and data analytics) in the context of novel reconfigurable architectures.\u003C/p>","2024-07-12T12:31:39.597Z","111",{"id":1535,"name":1536,"alternativeText":15,"caption":15,"width":1537,"height":1399,"formats":1538,"hash":1556,"ext":760,"mime":763,"size":1557,"url":1558,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1559,"updatedAt":1560},82,"Antonio Tumeo.jpg",942,{"small":1539,"medium":1545,"thumbnail":1551},{"ext":760,"url":1540,"hash":1541,"mime":763,"name":1542,"path":15,"size":1543,"width":1544,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Antonio_Tumeo_efacbb247c.jpg","small_Antonio_Tumeo_efacbb247c","small_Antonio Tumeo.jpg",39.75,491,{"ext":760,"url":1546,"hash":1547,"mime":763,"name":1548,"path":15,"size":1549,"width":1550,"height":655},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/medium_Antonio_Tumeo_efacbb247c.jpg","medium_Antonio_Tumeo_efacbb247c","medium_Antonio Tumeo.jpg",77.31,736,{"ext":760,"url":1552,"hash":1553,"mime":763,"name":1554,"path":15,"size":1555,"width":1272,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Antonio_Tumeo_efacbb247c.jpg","thumbnail_Antonio_Tumeo_efacbb247c","thumbnail_Antonio Tumeo.jpg",5.6,"Antonio_Tumeo_efacbb247c",106.46,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Antonio_Tumeo_efacbb247c.jpg","2024-07-12T12:31:21.646Z","2024-07-12T12:31:38.650Z",[],"-83","-86",{"id":200,"session":1565},{"id":200,"title":1566,"teaser":1567,"body":45,"createdAt":1568,"updatedAt":1569,"publishedAt":1570,"url_path_id":1571,"contacts":1572,"url_path":1600},"Are LLMs Any Good for High-Level Synthesis?","\u003Cp style=\"text-align:justify;\">As the demand for custom hardware accelerators grows, the need for rapid and efficient design methodologies becomes critical. The  escalating complexity of integrated circuits and the increasing demand for faster and more energy-efficient designs necessitate innovative  methodologies in High-Level Synthesis (HLS). Large Language Models (LLMs) have demonstrated their ability to automate various aspects of  computational tasks, including programming and software engineering. This paper investigates the potential of LLMs to streamline the HLS process  from high-level languages to hardware descriptions, with implications for applications such as AI acceleration, embedded systems, and high \u003Cbr>performance computing. We survey the state-of-the-art on using LLMs in the HLS process and conduct experiments comparing Verilog designs  generated from C/C++ using a standard HLS tool (e.g., Vitis HLS) with several LLM-based approaches. These approaches include direct LLM translation  of C/C++ benchmarks to Verilog and the use of LLMs to interpret natural language specifications into both benchmarks and Verilog code. Our  evaluation aims to assess the quality and efficiency of designs produced by each methodology. This study aims to illuminate the role of LLMs in HLS,  identifying the approaches that yield the most optimized hardware designs.\u003C/p>","2024-07-12T12:37:50.916Z","2024-07-12T12:37:52.393Z","2024-07-12T12:37:52.388Z","115",[1573],{"id":153,"name":1574,"committee":15,"position":15,"affiliation":1575,"email":15,"biography":1576,"createdAt":1577,"updatedAt":1578,"url_path_id":1579,"contactPhoto":1580,"socialLinks":1598,"url_path":1599},"Tosiron Adegbija","University of Arizona, USA","\u003Cp style=\"text-align:justify;\">Tosiron Adegbija is an Associate Professor of Electrical and Computer Engineering at the University of Arizona. He earned his Ph.D. and M.S.  in Electrical and Computer Engineering from the University of Florida, and his B.Eng in Electrical Engineering from the University of Ilorin, Nigeria.  His research interests are in brain-inspired computing, adaptable computing, hardware/software co-design of spiking neural networks, high-level  synthesis, and domain-specific architectures. He currently serves as Associate Editor for the IEEE Transactions on Computers and IEEE Embedded  Systems Letters and has served on Technical Program Committees (TPC) and Organizing Committees for numerous IEEE and ACM conferences. He  is a recipient of the National Science Foundation CAREER Award and is a Senior Member of the IEEE.\u003C/p>","2024-07-12T12:32:25.797Z","2024-07-12T12:34:05.147Z","112",{"id":1581,"name":1582,"alternativeText":15,"caption":15,"width":1583,"height":1584,"formats":1585,"hash":1593,"ext":1587,"mime":763,"size":1594,"url":1595,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1596,"updatedAt":1597},83,"Tosiron Adegbija.jpeg",301,295,{"thumbnail":1586},{"ext":1587,"url":1588,"hash":1589,"mime":763,"name":1590,"path":15,"size":1591,"width":1592,"height":622},".jpeg","https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Tosiron_Adegbija_143919b552.jpeg","thumbnail_Tosiron_Adegbija_143919b552","thumbnail_Tosiron Adegbija.jpeg",4.36,159,"Tosiron_Adegbija_143919b552",11.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Tosiron_Adegbija_143919b552.jpeg","2024-07-12T12:32:39.333Z","2024-07-12T12:32:53.407Z",[],"-84","-87",{"id":324,"session":1602},{"id":324,"title":1603,"teaser":1604,"body":45,"createdAt":1605,"updatedAt":1606,"publishedAt":1607,"url_path_id":1608,"contacts":1609,"url_path":1636},"Higher(er) Level Synthesis: Can HLS Tools Benefit from LLMs","\u003Cp style=\"text-align:justify;\">High Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This talk  investigates Large Language Models (LLMs) for refactoring C code into HLS-compatible formats. We present several case studies using an LLM to  rewrite C code for NIST 800-22 randomness tests, a QuickSort algorithm and AES-128 into HLS-synthesizable c. The LLM iteratively transforms the C  code guided by user prompts, implementing functions like streaming data and hardware-specific signals. This evaluation demonstrates the LLM's  potential to assist hardware design refactoring regular C code into HLS synthesizable C code. Joint work with Luca Collini and Ramesh Karri.\u003C/p>","2024-07-12T12:38:37.406Z","2024-07-12T12:38:39.008Z","2024-07-12T12:38:39.002Z","116",[1610],{"id":371,"name":1611,"committee":15,"position":15,"affiliation":1612,"email":15,"biography":1613,"createdAt":1614,"updatedAt":1615,"url_path_id":1616,"contactPhoto":1617,"socialLinks":1634,"url_path":1635},"Siddharth Garg","NYU, USA","\u003Cp style=\"text-align:justify;\">Siddarth Garg is currently the Institute Associate Professor of ECE at NYU Tandon, where he leads the EnSuRe Research group  (https://wp.nyu.edu/ensure_group/). Prior to that he was in Assistant Professor also in ECE from 2014-2020, and an Assistant Professor of ECE at  the Unversity of Waterloo from 2010-2014. His research interests are in machine learning, cyber-security and computer hardware design. \u003C/p>\u003Cp style=\"text-align:justify;\">He received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2009, and a B.Tech. degree in Electrical  Enginerring from the Indian Institute of Technology Madras. In 2016, Siddharth was listed in Popular Science Magazine's annual list of \"Brilliant 10\"  researchers. Siddharth has received the NSF CAREER Award (2015), and paper awards at the IEEE Symposium on Security and Privacy (S&P) 2016,  USENIX Security Symposium 2013, at the Semiconductor Research Consortium TECHCON in 2010, and the International Symposium on Quality in  Electronic Design (ISQED) in 2009. Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for  outstanding thesis contributions and service to the community. He serves on the technical program committee of several top conferences in the  area of computer engineering and computer hardware and has served as a reviewer for several IEEE and ACM journals. \u003C/p>","2024-07-12T12:34:49.175Z","2024-07-12T12:35:37.994Z","113",{"id":582,"name":1618,"alternativeText":15,"caption":15,"width":1619,"height":1619,"formats":1620,"hash":1630,"ext":760,"mime":763,"size":1631,"url":1632,"previewUrl":15,"provider":22,"provider_metadata":15,"createdAt":1633,"updatedAt":1633},"Siddarth Garg.jpg",543,{"small":1621,"thumbnail":1625},{"ext":760,"url":1622,"hash":1623,"mime":763,"name":1624,"path":15,"size":1309,"width":648,"height":648},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/small_Siddarth_Garg_f126b7bb08.jpg","small_Siddarth_Garg_f126b7bb08","small_Siddarth Garg.jpg",{"ext":760,"url":1626,"hash":1627,"mime":763,"name":1628,"path":15,"size":1629,"width":622,"height":622},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/thumbnail_Siddarth_Garg_f126b7bb08.jpg","thumbnail_Siddarth_Garg_f126b7bb08","thumbnail_Siddarth Garg.jpg",4.17,"Siddarth_Garg_f126b7bb08",26.16,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iccad24/Siddarth_Garg_f126b7bb08.jpg","2024-07-12T12:35:34.716Z",[],"-85","-88",{"data":1638,"meta":1644},{"id":324,"heading":1459,"createdAt":1639,"updatedAt":1640,"publishedAt":1641,"url_path_id":1642,"url_path":1643,"contentType":79},"2024-07-12T12:26:18.230Z","2024-07-12T13:19:33.116Z","2024-07-12T12:26:22.362Z","108","/ss2",{},1778851353037]